VHDL
Respositories
|
Total
/search/repositories?q=language:VHDL |
13560 |
|---|---|
|
New
/search/repositories?q=language:VHDL+created:2018-08-17 |
13 |
|
Increase rate
( New / Total ) * 100 |
0.10% |
|
Update
/search/repositories?q=language:VHDL+pushed:2018-08-17 |
43 |
|---|---|
|
Update Rate
( Update / Total ) * 100 |
0.32% |
|
Sleeping
/search/repositories?q=language:VHDL+pushed:<2017-08-17 |
8519 |
| Star 1000+
/search/repositories?q=language:VHDL+stars:>=1000 |
0 |
|---|---|
| Star 100+
/search/repositories?q=language:VHDL+stars:>=100 |
17 |
| Sum stars of Top 30 repos
sum ( repos.stars ) |
6426 |
| Fork 1000+ Repos
/search/repositories?q=language:VHDL+forks:>=1000 |
0 |
|---|---|
| Fork 100+
/search/repositories?q=language:VHDL+forks:>=100 |
6 |
| Sum forks of Top 30 repos
sum ( repos.forks ) |
2484 |
Top Star Repos
/search/repositories?q=language:VHDL&sort=stars&order=desc&per_page=30
-
774A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards.
699A work-in-progress for what is to be a software-free web server for static content.
608Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
516VHDL 2008/93/87 simulator
380GPL v3 2D/3D graphics engine in verilog
356Community created parallella projects
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354Parallella board design files
229VUnit is a unit testing framework for VHDL/SystemVerilog
220GameCube Digital AV converter
214Core sources and tools for the MIST board
197IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
187Arduino MIPI DSI Shield
169RISC-V by VectorBlox
166A 32-bit RISC-V / MIPS ISA retargetable CPU core
160Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer
122Space Invaders game implemented with VHDL
119An implementation of DisplayPort protocol for FPGAs
96Original hand-coded firmware for the HDMI2USB - HDMI/DVI Capture - project
84FPGA-based HDMI ambient lighting
81A pipelined RISCV implementation in VHDL
80The Zylin ZPU
76Open Source 4k CSI-2 Rx core for Xilinx FPGAs
71A simple RISC-V processor for use in FPGA designs.
70ZPUino HDL implementation
70Open Source VHDL Verification Library and Methodology - for very efficient VHDL verification of FPGA and ASIC - resulting also in a significant quality improvement
68Library of VHDL components that are useful in larger designs.
68Yet Another Forth Core...
65A repository of IPs for hardware computer vision (FPGA)
New Repos
/search/repositories?q=language:VHDL+created:2018-08-17&sort=stars&order=desc&per_page=12
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0MPSI Technologies modular vision demonstrator FPGA sub-system code
Users
Total /search/users?q=language:VHDL
3561 Followers 100+ /search/users?q=language:VHDL+followers:>=100
0 Repos per User repos.Total / users.Total
3.81 Most Followed
/search/users?q=language:VHDL+&sort=followers&order=desc&per_page=24
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