Updated : 2018-02-23 00:19:46 UTC

Respositories

Counts
Total

/search/repositories?q=language:VHDL

11343
New

/search/repositories?q=language:VHDL+created:2018-02-22

23
Increase rate

( New / Total ) * 100

0.20%
Activity
Update

/search/repositories?q=language:VHDL+pushed:2018-02-22

64
Update Rate

( Update / Total ) * 100

0.56%
Sleeping

/search/repositories?q=language:VHDL+pushed:<2017-02-22

7070
Stars
Star 1000+

/search/repositories?q=language:VHDL+stars:>=1000

0
Star 100+

/search/repositories?q=language:VHDL+stars:>=100

17
Sum stars of Top 30 repos

sum ( repos.stars )

5723
Forks
Fork 1000+ Repos

/search/repositories?q=language:VHDL+forks:>=1000

0
Fork 100+

/search/repositories?q=language:VHDL+forks:>=100

5
Sum forks of Top 30 repos

sum ( repos.forks )

2158

Top Star Repos

/search/repositories?q=language:VHDL&sort=stars&order=desc&per_page=30

  1. 697
    A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards.
  2. 688
    A work-in-progress for what is to be a software-free web server for static content.
  3. 523
    Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
  4. 406
    VHDL 2008/93/87 simulator
  5. 365
    GPL v3 2D/3D graphics engine in verilog
  6. 347
    Community created parallella projects
  1. 341
    Parallella board design files
  2. 201
    GameCube Digital AV converter
  3. 193
    Core sources and tools for the MIST board
  4. 172
    VUnit is a unit testing framework for VHDL/SystemVerilog
  5. 164
    Arduino MIPI DSI Shield
  6. 159
    IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universit├Ąt Dresden, Germany
  7. 147
    RISC-V by VectorBlox
  8. 136
    Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer
  9. 130
    A 32-bit RISC-V / MIPS ISA retargetable CPU core
  10. 118
    Space Invaders game implemented with VHDL
  11. 104
    An implementation of DisplayPort protocol for FPGAs
  12. 96
    Original hand-coded firmware for the HDMI2USB - HDMI/DVI Capture - project
  13. 78
    FPGA-based HDMI ambient lighting
  14. 77
    A pipelined RISCV implementation in VHDL
  15. 67
    Yet Another Forth Core...
  16. 66
    ZPUino HDL implementation
  17. 64
    The Zylin ZPU
  18. 62
    A repository of IPs for hardware computer vision (FPGA)
  19. 57
    TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. Designed to run on miniSpartan6+.
  20. 56
    Library of VHDL components that are useful in larger designs.
  21. 55
    A Bitcoin miner for the Zynq chip utilizing the Zedboard.
  22. 51
    VHDL Package for Sublime Text

New Repos

/search/repositories?q=language:VHDL+created:2018-02-22&sort=stars&order=desc&per_page=12

Users

Total

/search/users?q=language:VHDL

3002
Followers 100+

/search/users?q=language:VHDL+followers:>=100

0
Repos per User

repos.Total / users.Total

3.78