VHDL
Respositories
|
Total
/search/repositories?q=language:VHDL |
12227 |
|---|---|
|
New
/search/repositories?q=language:VHDL+created:2018-04-24 |
21 |
|
Increase rate
( New / Total ) * 100 |
0.17% |
|
Update
/search/repositories?q=language:VHDL+pushed:2018-04-24 |
96 |
|---|---|
|
Update Rate
( Update / Total ) * 100 |
0.79% |
|
Sleeping
/search/repositories?q=language:VHDL+pushed:<2017-04-24 |
7596 |
| Star 1000+
/search/repositories?q=language:VHDL+stars:>=1000 |
0 |
|---|---|
| Star 100+
/search/repositories?q=language:VHDL+stars:>=100 |
17 |
| Sum stars of Top 30 repos
sum ( repos.stars ) |
5981 |
| Fork 1000+ Repos
/search/repositories?q=language:VHDL+forks:>=1000 |
0 |
|---|---|
| Fork 100+
/search/repositories?q=language:VHDL+forks:>=100 |
6 |
| Sum forks of Top 30 repos
sum ( repos.forks ) |
2311 |
Top Star Repos
/search/repositories?q=language:VHDL&sort=stars&order=desc&per_page=30
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725A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards.
695A work-in-progress for what is to be a software-free web server for static content.
548Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
454VHDL 2008/93/87 simulator
371GPL v3 2D/3D graphics engine in verilog
351Community created parallella projects
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346Parallella board design files
209GameCube Digital AV converter
199Core sources and tools for the MIST board
191VUnit is a unit testing framework for VHDL/SystemVerilog
175IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
175Arduino MIPI DSI Shield
154RISC-V by VectorBlox
148Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer
140A 32-bit RISC-V / MIPS ISA retargetable CPU core
119Space Invaders game implemented with VHDL
109An implementation of DisplayPort protocol for FPGAs
96Original hand-coded firmware for the HDMI2USB - HDMI/DVI Capture - project
80A pipelined RISCV implementation in VHDL
80FPGA-based HDMI ambient lighting
68Yet Another Forth Core...
68ZPUino HDL implementation
66The Zylin ZPU
64A repository of IPs for hardware computer vision (FPGA)
62Library of VHDL components that are useful in larger designs.
61Open Source 4k CSI-2 Rx core for Xilinx FPGAs
59Open Source VHDL Verification Component Framework for making structured VHDL testbenches for verification of FPGA and ASIC.
58A Bitcoin miner for the Zynq chip utilizing the Zedboard.
New Repos
/search/repositories?q=language:VHDL+created:2018-04-24&sort=stars&order=desc&per_page=12
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0Small LIW/VLIW (long / very long instruction word) processor core built for my thesis project and for further personal research on processor architectures and the implementation of them.
Users
Total /search/users?q=language:VHDL
3282 Followers 100+ /search/users?q=language:VHDL+followers:>=100
0 Repos per User repos.Total / users.Total
3.73 Most Followed
/search/users?q=language:VHDL+&sort=followers&order=desc&per_page=24
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