Updated : 2018-12-19 00:19:50 UTC

Respositories

Counts
Total

/search/repositories?q=language:VHDL

15108
New

/search/repositories?q=language:VHDL+created:2018-12-18

10
Increase rate

( New / Total ) * 100

0.07%
Activity
Update

/search/repositories?q=language:VHDL+pushed:2018-12-18

60
Update Rate

( Update / Total ) * 100

0.40%
Sleeping

/search/repositories?q=language:VHDL+pushed:<2017-12-18

9677
Stars
Star 1000+

/search/repositories?q=language:VHDL+stars:>=1000

0
Star 100+

/search/repositories?q=language:VHDL+stars:>=100

18
Sum stars of Top 30 repos

sum ( repos.stars )

6988
Forks
Fork 1000+ Repos

/search/repositories?q=language:VHDL+forks:>=1000

0
Fork 100+

/search/repositories?q=language:VHDL+forks:>=100

7
Sum forks of Top 30 repos

sum ( repos.forks )

2668

Top Star Repos

/search/repositories?q=language:VHDL&sort=stars&order=desc&per_page=30

  1. 806
    A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards.
  2. 715
    A work-in-progress for what is to be a software-free web server for static content.
  3. 681
    Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
  4. 598
    VHDL 2008/93/87 simulator
  5. 408
    GPL v3 2D/3D graphics engine in verilog
  6. 361
    Parallella board design files
  1. 359
    Community created parallella projects
  2. 260
    VUnit is a unit testing framework for VHDL/SystemVerilog
  3. 243
    GameCube Digital AV converter
  4. 229
    Core sources and tools for the MIST board
  5. 220
    IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universit├Ąt Dresden, Germany
  6. 201
    Arduino MIPI DSI Shield
  7. 199
    A 32-bit RISC-V / MIPS ISA retargetable CPU core
  8. 192
    RISC-V by VectorBlox
  9. 170
    Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer
  10. 127
    An implementation of DisplayPort protocol for FPGAs
  11. 125
    Space Invaders game implemented with VHDL
  12. 110
    Open Source 4k CSI-2 Rx core for Xilinx FPGAs
  13. 97
    Original hand-coded firmware for the HDMI2USB - HDMI/DVI Capture - project
  14. 97
    Public repository for PicoEVB (Xilinx Artix XC7A50T based)
  15. 94
    A simple RISC-V processor for use in FPGA designs.
  16. 87
    The Zylin ZPU
  17. 86
    FPGA-based HDMI ambient lighting
  18. 82
    A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx.
  19. 82
    A pipelined RISCV implementation in VHDL
  20. 77
    Open Source VHDL Verification Library and Methodology - for very efficient VHDL verification of FPGA and ASIC - resulting also in a significant quality improvement
  21. 76
    Library of VHDL components that are useful in larger designs.
  22. 70
    ZPUino HDL implementation
  23. 68
    Yet Another Forth Core...
  24. 68
    A Bitcoin miner for the Zynq chip utilizing the Zedboard.

New Repos

/search/repositories?q=language:VHDL+created:2018-12-18&sort=stars&order=desc&per_page=12

Users

Total

/search/users?q=language:VHDL

3921
Followers 100+

/search/users?q=language:VHDL+followers:>=100

0
Repos per User

repos.Total / users.Total

3.85