VHDL

Top Star Repos

/search/repositories?q=language:VHDL&sort=stars&order=desc&per_page=30

1. ghdl / ghdl

   1032

   VHDL 2008/93/87 simulator
   
2. aws / aws-fpga

   960

   Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
   
3. progranism / Open-Source-FPGA-Bitcoin-Miner

   916

   A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards.
   
4. hamsternz / FPGA_Webserver

   741

   A work-in-progress for what is to be a software-free web server for static content.
   
5. asicguy / gplgpu

   485

   GPL v3 2D/3D graphics engine in verilog
   
6. parallella / parallella-hw

   380

   Parallella board design files
   

1. parallella / parallella-examples

   375

   Community created parallella projects
   
2. VUnit / vunit

   368

   VUnit is a unit testing framework for VHDL/SystemVerilog
   
3. mist-devel / mist-board

   320

   Core sources and tools for the MIST board
   
4. ikorb / gcvideo

   320

   GameCube Digital AV converter
   
5. VLSI-EDA / PoC

   315

   IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
   
6. nickg / nvc

   311

   VHDL compiler and simulator
   
7. f32c / f32c

   302

   A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz
   
8. twlostow / dsi-shield

   275

   Arduino MIPI DSI Shield
   
9. gtaylormb / opl3_fpga

   233

   Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer
   
10. daveshah1 / CSI2Rx

    226

    Open Source 4k CSI-2 Rx core for Xilinx FPGAs
    
11. howerj / forth-cpu

    193

    A Forth CPU and System on a Chip, based on the J1, written in VHDL
    
12. hamsternz / FPGA_DisplayPort

    173

    An implementation of DisplayPort protocol for FPGAs
    
13. ghdl / ghdl-yosys-plugin

    153

    VHDL synthesis (based on ghdl)
    
14. skordal / potato

    149

    A simple RISC-V processor for use in FPGA designs.
    
15. UVVM / UVVM

    149

    UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/
    
16. fabioperez / space-invaders-vhdl

    139

    Space Invaders game implemented with VHDL
    
17. openpower-cores / a2i

    134

    
    
18. bcattle / hardh264

    132

    A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx.
    
19. Ttl / vna2

    128

    Second version of homemade 30 MHz - 6 GHz VNA
    
20. OSVVM / OSVVM

    118

    Open Source VHDL Verification Methodology (OSVVM) Repository
    
21. abs-tudelft / fletcher

    117

    Fletcher: A framework to integrate FPGA accelerators with Apache Arrow
    
22. xesscorp / VHDL_Lib

    114

    Library of VHDL components that are useful in larger designs.
    
23. jofrfu / tinyTPU

    114

    Implementation of a Tensor Processing Unit for embedded systems and the IoT.
    
24. zylin / zpu

    106

    The Zylin ZPU
    

New Repos

/search/repositories?q=language:VHDL+created:2020-07-05&sort=stars&order=desc&per_page=12

• sir-drako / FPGA-based-Sudoku

  0

  Design and construction of an electronic Sudoku game using an Intel MAX 10 FPGA coded in VHDL and simulated with Quartus II.
• valeriot90 / ECS

  0

  Project for course of Electronic and Communication Systems
• GHJon / DE2-Accumulator

  0

  This project is aimed to create an accumulator using the Altera DE2 board. It does both unsigned and signed addition/subtraction and is dispalyed on the seven segment displays
• ThomasHornschuh / fusesoc_ghdl_test

  0

  Test core for testing fusesoc ghdl backend
• Seoyoung-Alice / GPR_system

  0

  Graduation project, multi ADC, GPR, RTS
• Liverio / sparse_CNN_inference_engine

  0

  RTL description of an inference engine for sparse CNNs
• GHJon / DE2-CPULite

  0

  This project mimics most of the properties of a 32-bit MIPS-Lite architecture. It includes an Instruction Register, ALU, temporary register control, Control logic, and data memory
• rocioruizruiz / Redes

  0
• GHJon / DE2-Bitwise-Operations

  0

  This project uses the Altera DE2 board to showcase the difference between a 1-bit comparator and an N-bit comparator and how they operate within each other.
• GHJon / DE2-Logical-Operations

  0

  This project goes through the logical operations done in simulation on Modelsim
• tonyre4 / maestriaFGPAproject

  0
• GHJon / DE2-Latches-and-FlipFlops

  0

  This project aims to gain a better understanding of latches and flip flops and their creation using VHDL code