VHDL
Respositories
|
Total
/search/repositories?q=language:VHDL |
14223 |
|---|---|
|
New
/search/repositories?q=language:VHDL+created:2018-10-22 |
11 |
|
Increase rate
( New / Total ) * 100 |
0.08% |
|
Update
/search/repositories?q=language:VHDL+pushed:2018-10-22 |
55 |
|---|---|
|
Update Rate
( Update / Total ) * 100 |
0.39% |
|
Sleeping
/search/repositories?q=language:VHDL+pushed:<2017-10-22 |
8963 |
| Star 1000+
/search/repositories?q=language:VHDL+stars:>=1000 |
0 |
|---|---|
| Star 100+
/search/repositories?q=language:VHDL+stars:>=100 |
17 |
| Sum stars of Top 30 repos
sum ( repos.stars ) |
6673 |
| Fork 1000+ Repos
/search/repositories?q=language:VHDL+forks:>=1000 |
0 |
|---|---|
| Fork 100+
/search/repositories?q=language:VHDL+forks:>=100 |
7 |
| Sum forks of Top 30 repos
sum ( repos.forks ) |
2575 |
Top Star Repos
/search/repositories?q=language:VHDL&sort=stars&order=desc&per_page=30
-
791A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards.
705A work-in-progress for what is to be a software-free web server for static content.
641Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
554VHDL 2008/93/87 simulator
395GPL v3 2D/3D graphics engine in verilog
359Parallella board design files
-
358Community created parallella projects
246VUnit is a unit testing framework for VHDL/SystemVerilog
227GameCube Digital AV converter
220Core sources and tools for the MIST board
209IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
194Arduino MIPI DSI Shield
180RISC-V by VectorBlox
178A 32-bit RISC-V / MIPS ISA retargetable CPU core
163Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer
124Space Invaders game implemented with VHDL
124An implementation of DisplayPort protocol for FPGAs
97Original hand-coded firmware for the HDMI2USB - HDMI/DVI Capture - project
97Open Source 4k CSI-2 Rx core for Xilinx FPGAs
85FPGA-based HDMI ambient lighting
82A pipelined RISCV implementation in VHDL
79The Zylin ZPU
78A simple RISC-V processor for use in FPGA designs.
75Open Source VHDL Verification Library and Methodology - for very efficient VHDL verification of FPGA and ASIC - resulting also in a significant quality improvement
73A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx.
69Library of VHDL components that are useful in larger designs.
69ZPUino HDL implementation
New Repos
/search/repositories?q=language:VHDL+created:2018-10-22&sort=stars&order=desc&per_page=12
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0FIR filter VHDL hardware design generator and raspberry pi framework that uses it.
Users
Total /search/users?q=language:VHDL
3732 Followers 100+ /search/users?q=language:VHDL+followers:>=100
0 Repos per User repos.Total / users.Total
3.81 Most Followed
/search/users?q=language:VHDL+&sort=followers&order=desc&per_page=24
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