VHDL
Respositories
|
Total
/search/repositories?q=language:VHDL |
18251 |
|---|---|
|
New
/search/repositories?q=language:VHDL+created:2019-08-20 |
11 |
|
Increase rate
( New / Total ) * 100 |
0.06% |
|
Update
/search/repositories?q=language:VHDL+pushed:2019-08-20 |
66 |
|---|---|
|
Update Rate
( Update / Total ) * 100 |
0.36% |
|
Sleeping
/search/repositories?q=language:VHDL+pushed:<2018-08-20 |
12352 |
| Star 1000+
/search/repositories?q=language:VHDL+stars:>=1000 |
0 |
|---|---|
| Star 100+
/search/repositories?q=language:VHDL+stars:>=100 |
24 |
| Sum stars of Top 30 repos
sum ( repos.stars ) |
8285 |
| Fork 1000+ Repos
/search/repositories?q=language:VHDL+forks:>=1000 |
0 |
|---|---|
| Fork 100+
/search/repositories?q=language:VHDL+forks:>=100 |
8 |
| Sum forks of Top 30 repos
sum ( repos.forks ) |
2722 |
Top Star Repos
/search/repositories?q=language:VHDL&sort=stars&order=desc&per_page=30
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865A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards.
810Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
760VHDL 2008/93/87 simulator
726A work-in-progress for what is to be a software-free web server for static content.
458GPL v3 2D/3D graphics engine in verilog
371Parallella board design files
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367Community created parallella projects
312VUnit is a unit testing framework for VHDL/SystemVerilog
292VHDL compiler and simulator
268Core sources and tools for the MIST board
268GameCube Digital AV converter
264IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
241A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz
240Arduino MIPI DSI Shield
225RISC-V by VectorBlox
203Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer
162Open Source 4k CSI-2 Rx core for Xilinx FPGAs
160A Forth CPU and System on a Chip, based on the J1, written in VHDL
154An implementation of DisplayPort protocol for FPGAs
133Space Invaders game implemented with VHDL
123Public repository for PicoEVB (Xilinx Artix XC7A50T based)
119A simple RISC-V processor for use in FPGA designs.
105A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx.
105UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement
98Original hand-coded firmware for the HDMI2USB - HDMI/DVI Capture - project
97The Zylin ZPU
96FPGA-based HDMI ambient lighting
90Library of VHDL components that are useful in larger designs.
87A pipelined RISCV implementation in VHDL
New Repos
/search/repositories?q=language:VHDL+created:2019-08-20&sort=stars&order=desc&per_page=12
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0Implementation of a Sort in VHDL. Formal verified using JasperGold
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0Sistemas Digitales 2, ESPOL, Ivan Campoverde-Elvis Ramirez
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0This repository holds the hardware project for the ORCA MPSoC platform.
Users
Total /search/users?q=language:VHDL
4635 Followers 100+ /search/users?q=language:VHDL+followers:>=100
0 Repos per User repos.Total / users.Total
3.94 Most Followed
/search/users?q=language:VHDL+&sort=followers&order=desc&per_page=24
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