Updated : 2018-06-24 00:19:44 UTC

Respositories

Counts
Total

/search/repositories?q=language:VHDL

13095
New

/search/repositories?q=language:VHDL+created:2018-06-23

1
Increase rate

( New / Total ) * 100

0.01%
Activity
Update

/search/repositories?q=language:VHDL+pushed:2018-06-23

33
Update Rate

( Update / Total ) * 100

0.25%
Sleeping

/search/repositories?q=language:VHDL+pushed:<2017-06-23

8183
Stars
Star 1000+

/search/repositories?q=language:VHDL+stars:>=1000

0
Star 100+

/search/repositories?q=language:VHDL+stars:>=100

17
Sum stars of Top 30 repos

sum ( repos.stars )

6227
Forks
Fork 1000+ Repos

/search/repositories?q=language:VHDL+forks:>=1000

0
Fork 100+

/search/repositories?q=language:VHDL+forks:>=100

5
Sum forks of Top 30 repos

sum ( repos.forks )

2401

Top Star Repos

/search/repositories?q=language:VHDL&sort=stars&order=desc&per_page=30

  1. 752
    A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards.
  2. 694
    A work-in-progress for what is to be a software-free web server for static content.
  3. 583
    Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
  4. 495
    VHDL 2008/93/87 simulator
  5. 376
    GPL v3 2D/3D graphics engine in verilog
  6. 353
    Community created parallella projects
  1. 351
    Parallella board design files
  2. 213
    GameCube Digital AV converter
  3. 210
    VUnit is a unit testing framework for VHDL/SystemVerilog
  4. 203
    Core sources and tools for the MIST board
  5. 187
    IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universit├Ąt Dresden, Germany
  6. 181
    Arduino MIPI DSI Shield
  7. 166
    RISC-V by VectorBlox
  8. 157
    Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer
  9. 155
    A 32-bit RISC-V / MIPS ISA retargetable CPU core
  10. 122
    Space Invaders game implemented with VHDL
  11. 114
    An implementation of DisplayPort protocol for FPGAs
  12. 96
    Original hand-coded firmware for the HDMI2USB - HDMI/DVI Capture - project
  13. 82
    FPGA-based HDMI ambient lighting
  14. 81
    A pipelined RISCV implementation in VHDL
  15. 74
    The Zylin ZPU
  16. 70
    ZPUino HDL implementation
  17. 68
    Yet Another Forth Core...
  18. 67
    Open Source 4k CSI-2 Rx core for Xilinx FPGAs
  19. 66
    Library of VHDL components that are useful in larger designs.
  20. 65
    A repository of IPs for hardware computer vision (FPGA)
  21. 65
    Open Source VHDL Verification Component Framework for making structured VHDL testbenches for verification of FPGA and ASIC.
  22. 62
    A simple RISC-V processor for use in FPGA designs.
  23. 62
    A Bitcoin miner for the Zynq chip utilizing the Zedboard.
  24. 57
    A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx.

New Repos

/search/repositories?q=language:VHDL+created:2018-06-23&sort=stars&order=desc&per_page=12

Users

Total

/search/users?q=language:VHDL

3440
Followers 100+

/search/users?q=language:VHDL+followers:>=100

0
Repos per User

repos.Total / users.Total

3.81