VHDL
Respositories
|
Total
/search/repositories?q=language:VHDL |
19016 |
|---|---|
|
New
/search/repositories?q=language:VHDL+created:2019-10-17 |
17 |
|
Increase rate
( New / Total ) * 100 |
0.09% |
|
Update
/search/repositories?q=language:VHDL+pushed:2019-10-17 |
89 |
|---|---|
|
Update Rate
( Update / Total ) * 100 |
0.47% |
|
Sleeping
/search/repositories?q=language:VHDL+pushed:<2018-10-17 |
12843 |
| Star 1000+
/search/repositories?q=language:VHDL+stars:>=1000 |
0 |
|---|---|
| Star 100+
/search/repositories?q=language:VHDL+stars:>=100 |
25 |
| Sum stars of Top 30 repos
sum ( repos.stars ) |
8633 |
| Fork 1000+ Repos
/search/repositories?q=language:VHDL+forks:>=1000 |
0 |
|---|---|
| Fork 100+
/search/repositories?q=language:VHDL+forks:>=100 |
8 |
| Sum forks of Top 30 repos
sum ( repos.forks ) |
2792 |
Top Star Repos
/search/repositories?q=language:VHDL&sort=stars&order=desc&per_page=30
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869A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards.
835Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
803VHDL 2008/93/87 simulator
727A work-in-progress for what is to be a software-free web server for static content.
463GPL v3 2D/3D graphics engine in verilog
372Parallella board design files
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369Community created parallella projects
322VUnit is a unit testing framework for VHDL/SystemVerilog
294VHDL compiler and simulator
281Core sources and tools for the MIST board
274GameCube Digital AV converter
271IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
263A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz
248Arduino MIPI DSI Shield
233RISC-V by VectorBlox
223A tiny Open POWER ISA softcore written in VHDL 2008
205Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer
172Open Source 4k CSI-2 Rx core for Xilinx FPGAs
163A Forth CPU and System on a Chip, based on the J1, written in VHDL
156An implementation of DisplayPort protocol for FPGAs
135Space Invaders game implemented with VHDL
131Public repository for PicoEVB (Xilinx Artix XC7A50T based)
123A simple RISC-V processor for use in FPGA designs.
110UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement
108A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx.
98Original hand-coded firmware for the HDMI2USB - HDMI/DVI Capture - project
98The Zylin ZPU
New Repos
/search/repositories?q=language:VHDL+created:2019-10-17&sort=stars&order=desc&per_page=12
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0Basic demonstration of a Microblaze system on the Basys board, with Soft Error Mitigation features.
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0It is a 2 player game in which there is 3x3 board on which either of player puts a 'X' or 'O'. In this a player with 3 consecutive 'X' or 'O' either vertically, horizontally or diagonally wins the game. it was implemented on Xilinx software on VHDL with VLSI Design Flow using mixed modelling structure.
Users
Total /search/users?q=language:VHDL
4801 Followers 100+ /search/users?q=language:VHDL+followers:>=100
0 Repos per User repos.Total / users.Total
3.96 Most Followed
/search/users?q=language:VHDL+&sort=followers&order=desc&per_page=24
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