Updated : 2019-02-23 00:19:41 UTC

Respositories

Counts
Total

/search/repositories?q=language:VHDL

15805
New

/search/repositories?q=language:VHDL+created:2019-02-22

16
Increase rate

( New / Total ) * 100

0.10%
Activity
Update

/search/repositories?q=language:VHDL+pushed:2019-02-22

73
Update Rate

( Update / Total ) * 100

0.46%
Sleeping

/search/repositories?q=language:VHDL+pushed:<2018-02-22

10263
Stars
Star 1000+

/search/repositories?q=language:VHDL+stars:>=1000

0
Star 100+

/search/repositories?q=language:VHDL+stars:>=100

20
Sum stars of Top 30 repos

sum ( repos.stars )

7258
Forks
Fork 1000+ Repos

/search/repositories?q=language:VHDL+forks:>=1000

0
Fork 100+

/search/repositories?q=language:VHDL+forks:>=100

8
Sum forks of Top 30 repos

sum ( repos.forks )

2672

Top Star Repos

/search/repositories?q=language:VHDL&sort=stars&order=desc&per_page=30

  1. 818
    A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards.
  2. 719
    Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
  3. 716
    A work-in-progress for what is to be a software-free web server for static content.
  4. 636
    VHDL 2008/93/87 simulator
  5. 416
    GPL v3 2D/3D graphics engine in verilog
  6. 365
    Parallella board design files
  1. 362
    Community created parallella projects
  2. 274
    VUnit is a unit testing framework for VHDL/SystemVerilog
  3. 249
    GameCube Digital AV converter
  4. 241
    Core sources and tools for the MIST board
  5. 229
    IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universit├Ąt Dresden, Germany
  6. 216
    A 32-bit RISC-V / MIPS ISA retargetable CPU core &amp; SoC, 1.63 DMIPS/MHz
  7. 208
    Arduino MIPI DSI Shield
  8. 204
    RISC-V by VectorBlox
  9. 175
    Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer
  10. 140
    An implementation of DisplayPort protocol for FPGAs
  11. 127
    Open Source 4k CSI-2 Rx core for Xilinx FPGAs
  12. 126
    Space Invaders game implemented with VHDL
  13. 105
    Public repository for PicoEVB (Xilinx Artix XC7A50T based)
  14. 103
    A simple RISC-V processor for use in FPGA designs.
  15. 95
    Original hand-coded firmware for the HDMI2USB - HDMI/DVI Capture - project
  16. 94
    FPGA-based HDMI ambient lighting
  17. 91
    The Zylin ZPU
  18. 88
    Open Source VHDL Verification Library and Methodology - for very efficient VHDL verification of FPGA and ASIC - resulting also in a significant quality improvement
  19. 85
    A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx.
  20. 82
    A pipelined RISCV implementation in VHDL
  21. 80
    Library of VHDL components that are useful in larger designs.
  22. 73
    ZPUino HDL implementation
  23. 71
    Second version of homemade 30 MHz - 6 GHz VNA
  24. 70
    Open Source VHDL Verification Methodology (OSVVM) Repository

New Repos

/search/repositories?q=language:VHDL+created:2019-02-22&sort=stars&order=desc&per_page=12

Users

Total

/search/users?q=language:VHDL

4061
Followers 100+

/search/users?q=language:VHDL+followers:>=100

0
Repos per User

repos.Total / users.Total

3.89