Updated : 2018-04-25 00:19:49 UTC

Respositories

Counts
Total

/search/repositories?q=language:VHDL

12227
New

/search/repositories?q=language:VHDL+created:2018-04-24

21
Increase rate

( New / Total ) * 100

0.17%
Activity
Update

/search/repositories?q=language:VHDL+pushed:2018-04-24

96
Update Rate

( Update / Total ) * 100

0.79%
Sleeping

/search/repositories?q=language:VHDL+pushed:<2017-04-24

7596
Stars
Star 1000+

/search/repositories?q=language:VHDL+stars:>=1000

0
Star 100+

/search/repositories?q=language:VHDL+stars:>=100

17
Sum stars of Top 30 repos

sum ( repos.stars )

5981
Forks
Fork 1000+ Repos

/search/repositories?q=language:VHDL+forks:>=1000

0
Fork 100+

/search/repositories?q=language:VHDL+forks:>=100

6
Sum forks of Top 30 repos

sum ( repos.forks )

2311

Top Star Repos

/search/repositories?q=language:VHDL&sort=stars&order=desc&per_page=30

  1. 725
    A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards.
  2. 695
    A work-in-progress for what is to be a software-free web server for static content.
  3. 548
    Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
  4. 454
    VHDL 2008/93/87 simulator
  5. 371
    GPL v3 2D/3D graphics engine in verilog
  6. 351
    Community created parallella projects
  1. 346
    Parallella board design files
  2. 209
    GameCube Digital AV converter
  3. 199
    Core sources and tools for the MIST board
  4. 191
    VUnit is a unit testing framework for VHDL/SystemVerilog
  5. 175
    IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
  6. 175
    Arduino MIPI DSI Shield
  7. 154
    RISC-V by VectorBlox
  8. 148
    Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer
  9. 140
    A 32-bit RISC-V / MIPS ISA retargetable CPU core
  10. 119
    Space Invaders game implemented with VHDL
  11. 109
    An implementation of DisplayPort protocol for FPGAs
  12. 96
    Original hand-coded firmware for the HDMI2USB - HDMI/DVI Capture - project
  13. 80
    A pipelined RISCV implementation in VHDL
  14. 80
    FPGA-based HDMI ambient lighting
  15. 68
    Yet Another Forth Core...
  16. 68
    ZPUino HDL implementation
  17. 66
    The Zylin ZPU
  18. 64
    A repository of IPs for hardware computer vision (FPGA)
  19. 62
    Library of VHDL components that are useful in larger designs.
  20. 61
    Open Source 4k CSI-2 Rx core for Xilinx FPGAs
  21. 59
    Open Source VHDL Verification Component Framework for making structured VHDL testbenches for verification of FPGA and ASIC.
  22. 58
    A Bitcoin miner for the Zynq chip utilizing the Zedboard.
  23. 55
    A simple RISC-V processor for use in FPGA designs.
  24. 55
    TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. Designed to run on miniSpartan6+.

New Repos

/search/repositories?q=language:VHDL+created:2018-04-24&sort=stars&order=desc&per_page=12

Users

Total

/search/users?q=language:VHDL

3282
Followers 100+

/search/users?q=language:VHDL+followers:>=100

0
Repos per User

repos.Total / users.Total

3.73