VHDL
Respositories
|
Total
/search/repositories?q=language:VHDL |
16750 |
|---|---|
|
New
/search/repositories?q=language:VHDL+created:2019-04-19 |
7 |
|
Increase rate
( New / Total ) * 100 |
0.04% |
|
Update
/search/repositories?q=language:VHDL+pushed:2019-04-19 |
66 |
|---|---|
|
Update Rate
( Update / Total ) * 100 |
0.39% |
|
Sleeping
/search/repositories?q=language:VHDL+pushed:<2018-04-19 |
10905 |
| Star 1000+
/search/repositories?q=language:VHDL+stars:>=1000 |
0 |
|---|---|
| Star 100+
/search/repositories?q=language:VHDL+stars:>=100 |
22 |
| Sum stars of Top 30 repos
sum ( repos.stars ) |
7814 |
| Fork 1000+ Repos
/search/repositories?q=language:VHDL+forks:>=1000 |
0 |
|---|---|
| Fork 100+
/search/repositories?q=language:VHDL+forks:>=100 |
8 |
| Sum forks of Top 30 repos
sum ( repos.forks ) |
2821 |
Top Star Repos
/search/repositories?q=language:VHDL&sort=stars&order=desc&per_page=30
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829A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards.
753Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
720A work-in-progress for what is to be a software-free web server for static content.
685VHDL 2008/93/87 simulator
432GPL v3 2D/3D graphics engine in verilog
367Community created parallella projects
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367Parallella board design files
287VUnit is a unit testing framework for VHDL/SystemVerilog
278VHDL compiler and simulator
257GameCube Digital AV converter
254Core sources and tools for the MIST board
239IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
224A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz
221Arduino MIPI DSI Shield
209RISC-V by VectorBlox
191Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer
148A Forth CPU and System on a Chip, based on the J1, written in VHDL
145An implementation of DisplayPort protocol for FPGAs
139Open Source 4k CSI-2 Rx core for Xilinx FPGAs
130Space Invaders game implemented with VHDL
116Public repository for PicoEVB (Xilinx Artix XC7A50T based)
111A simple RISC-V processor for use in FPGA designs.
97Original hand-coded firmware for the HDMI2USB - HDMI/DVI Capture - project
96FPGA-based HDMI ambient lighting
93The Zylin ZPU
93Open Source VHDL Verification Library and Methodology - for very efficient VHDL verification of FPGA and ASIC - resulting also in a significant quality improvement
91A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx.
86A pipelined RISCV implementation in VHDL
New Repos
/search/repositories?q=language:VHDL+created:2019-04-19&sort=stars&order=desc&per_page=12
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0This is a set of AER (Address Event Representation) tools to monitor, log and play an stream of aer data
Users
Total /search/users?q=language:VHDL
4280 Followers 100+ /search/users?q=language:VHDL+followers:>=100
0 Repos per User repos.Total / users.Total
3.91 Most Followed
/search/users?q=language:VHDL+&sort=followers&order=desc&per_page=24
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