VHDL
Respositories
|
Total
/search/repositories?q=language:VHDL |
15805 |
|---|---|
|
New
/search/repositories?q=language:VHDL+created:2019-02-22 |
16 |
|
Increase rate
( New / Total ) * 100 |
0.10% |
|
Update
/search/repositories?q=language:VHDL+pushed:2019-02-22 |
73 |
|---|---|
|
Update Rate
( Update / Total ) * 100 |
0.46% |
|
Sleeping
/search/repositories?q=language:VHDL+pushed:<2018-02-22 |
10263 |
| Star 1000+
/search/repositories?q=language:VHDL+stars:>=1000 |
0 |
|---|---|
| Star 100+
/search/repositories?q=language:VHDL+stars:>=100 |
20 |
| Sum stars of Top 30 repos
sum ( repos.stars ) |
7258 |
| Fork 1000+ Repos
/search/repositories?q=language:VHDL+forks:>=1000 |
0 |
|---|---|
| Fork 100+
/search/repositories?q=language:VHDL+forks:>=100 |
8 |
| Sum forks of Top 30 repos
sum ( repos.forks ) |
2672 |
Top Star Repos
/search/repositories?q=language:VHDL&sort=stars&order=desc&per_page=30
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818A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards.
719Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
716A work-in-progress for what is to be a software-free web server for static content.
636VHDL 2008/93/87 simulator
416GPL v3 2D/3D graphics engine in verilog
365Parallella board design files
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362Community created parallella projects
274VUnit is a unit testing framework for VHDL/SystemVerilog
249GameCube Digital AV converter
241Core sources and tools for the MIST board
229IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
216A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz
208Arduino MIPI DSI Shield
204RISC-V by VectorBlox
175Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer
140An implementation of DisplayPort protocol for FPGAs
127Open Source 4k CSI-2 Rx core for Xilinx FPGAs
126Space Invaders game implemented with VHDL
105Public repository for PicoEVB (Xilinx Artix XC7A50T based)
103A simple RISC-V processor for use in FPGA designs.
95Original hand-coded firmware for the HDMI2USB - HDMI/DVI Capture - project
94FPGA-based HDMI ambient lighting
91The Zylin ZPU
88Open Source VHDL Verification Library and Methodology - for very efficient VHDL verification of FPGA and ASIC - resulting also in a significant quality improvement
85A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx.
82A pipelined RISCV implementation in VHDL
80Library of VHDL components that are useful in larger designs.
New Repos
/search/repositories?q=language:VHDL+created:2019-02-22&sort=stars&order=desc&per_page=12
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0A synthesizable VHDL based cycle accurate PERformance SImulation Architecture for Networks-on-chip. PERSIAN-NoC is a parameterized RTL model for evaluating the performance factors of NoC based interconnection networks.
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0VHDL codes to generate GPS L1 C/A and Galileo E1OS and E5 PRNs and signals
Users
Total /search/users?q=language:VHDL
4061 Followers 100+ /search/users?q=language:VHDL+followers:>=100
0 Repos per User repos.Total / users.Total
3.89 Most Followed
/search/users?q=language:VHDL+&sort=followers&order=desc&per_page=24
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