VHDL
Respositories
|
Total
/search/repositories?q=language:VHDL |
13095 |
|---|---|
|
New
/search/repositories?q=language:VHDL+created:2018-06-23 |
1 |
|
Increase rate
( New / Total ) * 100 |
0.01% |
|
Update
/search/repositories?q=language:VHDL+pushed:2018-06-23 |
33 |
|---|---|
|
Update Rate
( Update / Total ) * 100 |
0.25% |
|
Sleeping
/search/repositories?q=language:VHDL+pushed:<2017-06-23 |
8183 |
| Star 1000+
/search/repositories?q=language:VHDL+stars:>=1000 |
0 |
|---|---|
| Star 100+
/search/repositories?q=language:VHDL+stars:>=100 |
17 |
| Sum stars of Top 30 repos
sum ( repos.stars ) |
6227 |
| Fork 1000+ Repos
/search/repositories?q=language:VHDL+forks:>=1000 |
0 |
|---|---|
| Fork 100+
/search/repositories?q=language:VHDL+forks:>=100 |
5 |
| Sum forks of Top 30 repos
sum ( repos.forks ) |
2401 |
Top Star Repos
/search/repositories?q=language:VHDL&sort=stars&order=desc&per_page=30
-
752A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards.
694A work-in-progress for what is to be a software-free web server for static content.
583Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
495VHDL 2008/93/87 simulator
376GPL v3 2D/3D graphics engine in verilog
353Community created parallella projects
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351Parallella board design files
213GameCube Digital AV converter
210VUnit is a unit testing framework for VHDL/SystemVerilog
203Core sources and tools for the MIST board
187IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
181Arduino MIPI DSI Shield
166RISC-V by VectorBlox
157Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer
155A 32-bit RISC-V / MIPS ISA retargetable CPU core
122Space Invaders game implemented with VHDL
114An implementation of DisplayPort protocol for FPGAs
96Original hand-coded firmware for the HDMI2USB - HDMI/DVI Capture - project
82FPGA-based HDMI ambient lighting
81A pipelined RISCV implementation in VHDL
74The Zylin ZPU
70ZPUino HDL implementation
68Yet Another Forth Core...
67Open Source 4k CSI-2 Rx core for Xilinx FPGAs
66Library of VHDL components that are useful in larger designs.
65A repository of IPs for hardware computer vision (FPGA)
65Open Source VHDL Verification Component Framework for making structured VHDL testbenches for verification of FPGA and ASIC.
62A simple RISC-V processor for use in FPGA designs.
New Repos
/search/repositories?q=language:VHDL+created:2018-06-23&sort=stars&order=desc&per_page=12
-
0Space Invaders clone using assembly and the cal poly slo RAT Microprocessor
Users
Total /search/users?q=language:VHDL
3440 Followers 100+ /search/users?q=language:VHDL+followers:>=100
0 Repos per User repos.Total / users.Total
3.81 Most Followed
/search/users?q=language:VHDL+&sort=followers&order=desc&per_page=24
progranism