VHDL
Respositories
|
Total
/search/repositories?q=language:VHDL |
15108 |
|---|---|
|
New
/search/repositories?q=language:VHDL+created:2018-12-18 |
10 |
|
Increase rate
( New / Total ) * 100 |
0.07% |
|
Update
/search/repositories?q=language:VHDL+pushed:2018-12-18 |
60 |
|---|---|
|
Update Rate
( Update / Total ) * 100 |
0.40% |
|
Sleeping
/search/repositories?q=language:VHDL+pushed:<2017-12-18 |
9677 |
| Star 1000+
/search/repositories?q=language:VHDL+stars:>=1000 |
0 |
|---|---|
| Star 100+
/search/repositories?q=language:VHDL+stars:>=100 |
18 |
| Sum stars of Top 30 repos
sum ( repos.stars ) |
6988 |
| Fork 1000+ Repos
/search/repositories?q=language:VHDL+forks:>=1000 |
0 |
|---|---|
| Fork 100+
/search/repositories?q=language:VHDL+forks:>=100 |
7 |
| Sum forks of Top 30 repos
sum ( repos.forks ) |
2668 |
Top Star Repos
/search/repositories?q=language:VHDL&sort=stars&order=desc&per_page=30
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806A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards.
715A work-in-progress for what is to be a software-free web server for static content.
681Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
598VHDL 2008/93/87 simulator
408GPL v3 2D/3D graphics engine in verilog
361Parallella board design files
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359Community created parallella projects
260VUnit is a unit testing framework for VHDL/SystemVerilog
243GameCube Digital AV converter
229Core sources and tools for the MIST board
220IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
201Arduino MIPI DSI Shield
199A 32-bit RISC-V / MIPS ISA retargetable CPU core
192RISC-V by VectorBlox
170Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer
127An implementation of DisplayPort protocol for FPGAs
125Space Invaders game implemented with VHDL
110Open Source 4k CSI-2 Rx core for Xilinx FPGAs
97Original hand-coded firmware for the HDMI2USB - HDMI/DVI Capture - project
97Public repository for PicoEVB (Xilinx Artix XC7A50T based)
94A simple RISC-V processor for use in FPGA designs.
87The Zylin ZPU
86FPGA-based HDMI ambient lighting
82A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx.
82A pipelined RISCV implementation in VHDL
77Open Source VHDL Verification Library and Methodology - for very efficient VHDL verification of FPGA and ASIC - resulting also in a significant quality improvement
76Library of VHDL components that are useful in larger designs.
70ZPUino HDL implementation
68Yet Another Forth Core...
New Repos
/search/repositories?q=language:VHDL+created:2018-12-18&sort=stars&order=desc&per_page=12
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0VHDL implementation of a parametric Convolutional Code Generator
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0Semester project in Hardware Systems Modeling 1 at EPFL. Functional verification of a 16x8-bit FIFO using OSVVM.
Users
Total /search/users?q=language:VHDL
3921 Followers 100+ /search/users?q=language:VHDL+followers:>=100
0 Repos per User repos.Total / users.Total
3.85 Most Followed
/search/users?q=language:VHDL+&sort=followers&order=desc&per_page=24
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