( New / Total ) * 100
( Update / Total ) * 100
|Sum stars of Top 30 repos
sum ( repos.stars )
|Fork 1000+ Repos
|Sum forks of Top 30 repos
sum ( repos.forks )
Top Star Repos
881A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards.
871Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
850VHDL 2008/93/87 simulator
730A work-in-progress for what is to be a software-free web server for static content.
468GPL v3 2D/3D graphics engine in verilog
372Parallella board design files
369Community created parallella projects
334VUnit is a unit testing framework for VHDL/SystemVerilog
301VHDL compiler and simulator
290Core sources and tools for the MIST board
282GameCube Digital AV converter
282IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
276A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz
251Arduino MIPI DSI Shield
240RISC-V by VectorBlox
238A tiny Open POWER ISA softcore written in VHDL 2008
210Reverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer
178Open Source 4k CSI-2 Rx core for Xilinx FPGAs
166A Forth CPU and System on a Chip, based on the J1, written in VHDL
159An implementation of DisplayPort protocol for FPGAs
138Space Invaders game implemented with VHDL
132A simple RISC-V processor for use in FPGA designs.
120UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. ***NOTE*** Modelsim/Questa 2019.2 has a bug. Do not use this version.
115A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx.
107Second version of homemade 30 MHz - 6 GHz VNA
99Original hand-coded firmware for the HDMI2USB - HDMI/DVI Capture - project
99Library of VHDL components that are useful in larger designs.
4997 Followers 100+
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