SystemVerilog

Updated : 2019-08-21 00:47:13 UTC

Respositories

Counts
Total

/search/repositories?q=language:SystemVerilog

3790
New

/search/repositories?q=language:SystemVerilog+created:2019-08-20

3
Increase rate

( New / Total ) * 100

0.08%
Activity
Update

/search/repositories?q=language:SystemVerilog+pushed:2019-08-20

21
Update Rate

( Update / Total ) * 100

0.55%
Sleeping

/search/repositories?q=language:SystemVerilog+pushed:<2018-08-20

2198
Stars
Star 1000+

/search/repositories?q=language:SystemVerilog+stars:>=1000

0
Star 100+

/search/repositories?q=language:SystemVerilog+stars:>=100

12
Sum stars of Top 30 repos

sum ( repos.stars )

4178
Forks
Fork 1000+ Repos

/search/repositories?q=language:SystemVerilog+forks:>=1000

0
Fork 100+

/search/repositories?q=language:SystemVerilog+forks:>=100

0
Sum forks of Top 30 repos

sum ( repos.forks )

1215

Top Star Repos

/search/repositories?q=language:SystemVerilog&sort=stars&order=desc&per_page=30

  1. 691
    A directory of Western Digital’s RISC-V SweRV Cores
  2. 522
    Ariane is a 6-stage RISC-V CPU capable of booting Linux
  3. 398
    The root repo for lowRISC project and FPGA demos.
  4. 303
    An exploration of log domain "alternative floating point" for hardware ML/AI accelerators.
  5. 246
    A Verilog synthesis flow for Minecraft redstone circuits
  6. 236
    RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU
  1. 204
    SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  2. 137
    training labs and examples
  3. 130
    RISC-V CPU Core
  4. 121
    Contains the code examples from The UVM Primer Book sorted by chapters.
  5. 107
    Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
  6. 103
    SV/UVM based open-source instruction generator for RISC-V processor verification
  7. 89
    CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  8. 75
    This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
  9. 71
    Reference examples and short projects using UVM Methodology
  10. 71
    Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
  11. 68
    This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
  12. 66
    Ultimate multigame cartridge for Nintendo Famicom
  13. 58
    Source code repo for UVM Tutorial for Candy Lovers
  14. 53
    Verilog code for a simple synth module; developed on TinyFPGA BX
  15. 46
    Public repository for uEVB
  16. 45
    AXI4 and AXI4-Lite interface definitions and testbench utilities
  17. 44
    Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
  18. 42
    SweRV EH1 core
  19. 40
    a playground for xilinx zynq fpga experiments
  20. 40
    WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
  21. 40
    High performance embedded systems debug/reverse engineering platform
  22. 39
    RISC-V Rocket Core on Parallella &amp; ZedBoard Zynq FPGA Boards

New Repos

/search/repositories?q=language:SystemVerilog+created:2019-08-20&sort=stars&order=desc&per_page=12

Users

Total

/search/users?q=language:SystemVerilog

1163
Followers 100+

/search/users?q=language:SystemVerilog+followers:>=100

0
Repos per User

repos.Total / users.Total

3.26