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Top Star Repos
316Ariane is a 6-stage RISC-V CPU
311The root repo for lowRISC project and FPGA demos.
149A Verilog synthesis flow for Minecraft redstone circuits
132SCR1 is a high-quality open-source RISC-V MCU core in Verilog
123RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU
95Contains the code examples from The UVM Primer Book sorted by chapters.
92RISC-V CPU Core
91training labs and examples
9032-bit RISC-V system on chip for iCE40 FPGAs
55Ultimate multigame cartridge for Nintendo Famicom
54This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
52Reference examples and short projects using UVM Methodology
52Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
50CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
40Hardware of sampling model
40Source code repo for UVM Tutorial for Candy Lovers
36Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
35This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
35Verilog code for a simple synth module; developed on TinyFPGA BX
32RISC-V port to Parallella Board
31a playground for xilinx zynq fpga experiments
28Examples and reference for System Verilog Assertions
26openHMC - an open source Hybrid Memory Cube Controller
26SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)
24WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
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