SystemVerilog

Updated : 2018-08-18 00:46:59 UTC

Respositories

Counts
Total

/search/repositories?q=language:SystemVerilog

2573
New

/search/repositories?q=language:SystemVerilog+created:2018-08-17

4
Increase rate

( New / Total ) * 100

0.16%
Activity
Update

/search/repositories?q=language:SystemVerilog+pushed:2018-08-17

16
Update Rate

( Update / Total ) * 100

0.62%
Sleeping

/search/repositories?q=language:SystemVerilog+pushed:<2017-08-17

1360
Stars
Star 1000+

/search/repositories?q=language:SystemVerilog+stars:>=1000

0
Star 100+

/search/repositories?q=language:SystemVerilog+stars:>=100

5
Sum stars of Top 30 repos

sum ( repos.stars )

1871
Forks
Fork 1000+ Repos

/search/repositories?q=language:SystemVerilog+forks:>=1000

0
Fork 100+

/search/repositories?q=language:SystemVerilog+forks:>=100

0
Sum forks of Top 30 repos

sum ( repos.forks )

629

Top Star Repos

/search/repositories?q=language:SystemVerilog&sort=stars&order=desc&per_page=30

  1. 287
    Ariane is a 6-stage RISC-V CPU
  2. 284
    The root repo for lowRISC project and FPGA demos.
  3. 140
    A Verilog synthesis flow for Minecraft redstone circuits
  4. 113
    SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  5. 101
    RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU
  6. 87
    Contains the code examples from The UVM Primer Book sorted by chapters.
  1. 85
    training labs and examples
  2. 74
    RISC-V CPU Core
  3. 64
    32-bit RISC-V system on chip for iCE40 FPGAs
  4. 49
    Reference examples and short projects using UVM Methodology
  5. 48
    Ultimate multigame cartridge for Nintendo Famicom
  6. 46
    CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  7. 44
    Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
  8. 41
    This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
  9. 38
    Source code repo for UVM Tutorial for Candy Lovers
  10. 33
    Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
  11. 30
    a playground for xilinx zynq fpga experiments
  12. 28
    This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
  13. 28
    RISC-V port to Parallella Board
  14. 27
    Examples and reference for System Verilog Assertions
  15. 26
    SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)
  16. 25
    UVM agents
  17. 25
    openHMC - an open source Hybrid Memory Cube Controller
  18. 23
    a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially
  19. 19
    Verilog code for a simple synth module; developed on TinyFPGA BX
  20. 19
    Advanced Encryption Standard (AES) SystemVerilog Core
  21. 17
    An attribute grammar-based programming language for composable language extensions
  22. 17
    ZX Spectrum 128K for MIST Board

New Repos

/search/repositories?q=language:SystemVerilog+created:2018-08-17&sort=stars&order=desc&per_page=12

Users

Total

/search/users?q=language:SystemVerilog

817
Followers 100+

/search/users?q=language:SystemVerilog+followers:>=100

0
Repos per User

repos.Total / users.Total

3.15