SystemVerilog

Updated : 2018-04-19 00:47:05 UTC

Respositories

Counts
Total

/search/repositories?q=language:SystemVerilog

2240
New

/search/repositories?q=language:SystemVerilog+created:2018-04-18

7
Increase rate

( New / Total ) * 100

0.31%
Activity
Update

/search/repositories?q=language:SystemVerilog+pushed:2018-04-18

28
Update Rate

( Update / Total ) * 100

1.25%
Sleeping

/search/repositories?q=language:SystemVerilog+pushed:<2017-04-18

1121
Stars
Star 1000+

/search/repositories?q=language:SystemVerilog+stars:>=1000

0
Star 100+

/search/repositories?q=language:SystemVerilog+stars:>=100

2
Sum stars of Top 30 repos

sum ( repos.stars )

1513
Forks
Fork 1000+ Repos

/search/repositories?q=language:SystemVerilog+forks:>=1000

0
Fork 100+

/search/repositories?q=language:SystemVerilog+forks:>=100

0
Sum forks of Top 30 repos

sum ( repos.forks )

532

Top Star Repos

/search/repositories?q=language:SystemVerilog&sort=stars&order=desc&per_page=30

  1. 249
    The root repo for lowRISC project and FPGA demos.
  2. 243
    Ariane is a 6-stage RISC-V CPU
  3. 91
    SCR1 is an open-source RISC-V compatible MCU core
  4. 79
    training labs and examples
  5. 79
    A Verilog synthesis flow for Minecraft redstone circuits
  1. 72
    Contains the code examples from The UVM Primer Book sorted by chapters.
  2. 48
    RISC-V CPU Core
  3. 48
    Ultimate multigame cartridge for Nintendo Famicom
  4. 44
    32-bit RISC-V system on chip for iCE40 FPGAs
  5. 43
    Reference examples and short projects using UVM Methodology
  6. 34
    Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
  7. 32
    Source code repo for UVM Tutorial for Candy Lovers
  8. 31
    CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  9. 30
    a playground for xilinx zynq fpga experiments
  10. 30
    This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
  11. 29
    Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
  12. 27
    RISC-V port to Parallella Board
  13. 25
    Examples and reference for System Verilog Assertions
  14. 24
    openHMC - an open source Hybrid Memory Cube Controller
  15. 23
    UVM agents
  16. 21
    SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)
  17. 20
    a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially
  18. 17
    Advanced Encryption Standard (AES) SystemVerilog Core
  19. 16
    This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
  20. 16
    An attribute grammar-based programming language for composable language extensions
  21. 13
    UVM Examples
  22. 13
    A high-throughput VHDL and SystemVerilog implementation of AES-128 including scripts for a full front-end design process.
  23. 13
    SystemVerilog VIP for AMBA APB protocol

New Repos

/search/repositories?q=language:SystemVerilog+created:2018-04-18&sort=stars&order=desc&per_page=12

Users

Total

/search/users?q=language:SystemVerilog

722
Followers 100+

/search/users?q=language:SystemVerilog+followers:>=100

0
Repos per User

repos.Total / users.Total

3.10