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Top Star Repos
734A directory of Western Digital’s RISC-V SweRV Cores
647Ariane is a 6-stage RISC-V CPU capable of booting Linux
554OpenTitan: Open source silicon root of trust
440The root repo for lowRISC project and FPGA demos.
324An exploration of log domain "alternative floating point" for hardware ML/AI accelerators.
315RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU
308NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
274A Verilog synthesis flow for Minecraft redstone circuits
263SCR1 is a high-quality open-source RISC-V MCU core in Verilog
214Proving leftpad correct in a dozen different ways
211SV/UVM based instruction generator for RISC-V processor verification
205Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
164FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software
154training labs and examples
136RISC-V CPU Core
136Contains the code examples from The UVM Primer Book sorted by chapters.
136SweRV EH1 core
119RSD: RISC-V Out-of-Order Superscalar Processor
110CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
101This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
93This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
84Reference examples and short projects using UVM Methodology
78Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
76AXI4 and AXI4-Lite interface definitions and testbench utilities
72Ultimate multigame cartridge for Nintendo Famicom
67Source code repo for UVM Tutorial for Candy Lovers
1406 Followers 100+
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