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Top Star Repos
677A directory of Western Digital’s RISC-V SweRV Cores
486Ariane is a 6-stage RISC-V CPU capable of booting Linux
392The root repo for lowRISC project and FPGA demos.
296An exploration of log domain "alternative floating point" for hardware ML/AI accelerators.
232A Verilog synthesis flow for Minecraft redstone circuits
212RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU
193SCR1 is a high-quality open-source RISC-V MCU core in Verilog
127training labs and examples
125RISC-V CPU Core
117Contains the code examples from The UVM Primer Book sorted by chapters.
82CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
75Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
67Reference examples and short projects using UVM Methodology
67This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
65Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
59Ultimate multigame cartridge for Nintendo Famicom
56This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
54Source code repo for UVM Tutorial for Candy Lovers
49Verilog code for a simple synth module; developed on TinyFPGA BX
44Public repository for uEVB
44Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
41AXI4 and AXI4-Lite interface definitions and testbench utilities
40a playground for xilinx zynq fpga experiments
40High performance embedded systems debug/reverse engineering platform
39Hardware of sampling model
1093 Followers 100+
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