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Top Star Repos
648A directory of Western Digital’s RISC-V SweRV Cores
439Ariane is a 6-stage RISC-V CPU capable of booting Linux
372The root repo for lowRISC project and FPGA demos.
285An exploration of log domain "alternative floating point" for hardware ML/AI accelerators.
188A Verilog synthesis flow for Minecraft redstone circuits
186SCR1 is a high-quality open-source RISC-V MCU core in Verilog
184RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU
121RISC-V CPU Core
113training labs and examples
110Contains the code examples from The UVM Primer Book sorted by chapters.
72CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
63This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
62Reference examples and short projects using UVM Methodology
61Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
57Ultimate multigame cartridge for Nintendo Famicom
52This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
50Source code repo for UVM Tutorial for Candy Lovers
47Verilog code for a simple synth module; developed on TinyFPGA BX
41Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
40a playground for xilinx zynq fpga experiments
39Hardware of sampling model
38High performance embedded systems debug/reverse engineering platform
37WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
37RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
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