SystemVerilog

Updated : 2018-12-19 00:47:45 UTC

Respositories

Counts
Total

/search/repositories?q=language:SystemVerilog

2988
New

/search/repositories?q=language:SystemVerilog+created:2018-12-18

2
Increase rate

( New / Total ) * 100

0.07%
Activity
Update

/search/repositories?q=language:SystemVerilog+pushed:2018-12-18

14
Update Rate

( Update / Total ) * 100

0.47%
Sleeping

/search/repositories?q=language:SystemVerilog+pushed:<2017-12-18

1646
Stars
Star 1000+

/search/repositories?q=language:SystemVerilog+stars:>=1000

0
Star 100+

/search/repositories?q=language:SystemVerilog+stars:>=100

9
Sum stars of Top 30 repos

sum ( repos.stars )

2616
Forks
Fork 1000+ Repos

/search/repositories?q=language:SystemVerilog+forks:>=1000

0
Fork 100+

/search/repositories?q=language:SystemVerilog+forks:>=100

0
Sum forks of Top 30 repos

sum ( repos.forks )

799

Top Star Repos

/search/repositories?q=language:SystemVerilog&sort=stars&order=desc&per_page=30

  1. 344
    Ariane is a 6-stage RISC-V CPU capable of booting Linux
  2. 328
    The root repo for lowRISC project and FPGA demos.
  3. 250
    An exploration of log domain "alternative floating point" for hardware ML/AI accelerators.
  4. 163
    A Verilog synthesis flow for Minecraft redstone circuits
  5. 149
    SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  6. 142
    RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU
  1. 108
    32-bit RISC-V system on chip for iCE40 FPGAs
  2. 105
    RISC-V CPU Core
  3. 100
    Contains the code examples from The UVM Primer Book sorted by chapters.
  4. 93
    training labs and examples
  5. 88
    Spatial: &quot;Specify Parameterized Accelerators Through Inordinately Abstract Language&quot;
  6. 57
    This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
  7. 57
    CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  8. 56
    Ultimate multigame cartridge for Nintendo Famicom
  9. 55
    Reference examples and short projects using UVM Methodology
  10. 53
    Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
  11. 43
    Source code repo for UVM Tutorial for Candy Lovers
  12. 40
    This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
  13. 39
    Hardware of sampling model
  14. 38
    Verilog code for a simple synth module; developed on TinyFPGA BX
  15. 38
    Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
  16. 35
    a playground for xilinx zynq fpga experiments
  17. 33
    RISC-V Rocket Core on Parallella &amp; ZedBoard Zynq FPGA Boards
  18. 29
    WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
  19. 28
    Examples and reference for System Verilog Assertions
  20. 26
    UVM agents
  21. 26
    SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)
  22. 25
    openHMC - an open source Hybrid Memory Cube Controller

New Repos

/search/repositories?q=language:SystemVerilog+created:2018-12-18&sort=stars&order=desc&per_page=12

Users

Total

/search/users?q=language:SystemVerilog

904
Followers 100+

/search/users?q=language:SystemVerilog+followers:>=100

0
Repos per User

repos.Total / users.Total

3.31