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( Update / Total ) * 100
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Top Star Repos
705A directory of Western Digital’s RISC-V SweRV Cores
558Ariane is a 6-stage RISC-V CPU capable of booting Linux
407The root repo for lowRISC project and FPGA demos.
312An exploration of log domain "alternative floating point" for hardware ML/AI accelerators.
260RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU
255A Verilog synthesis flow for Minecraft redstone circuits
253NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
226SCR1 is a high-quality open-source RISC-V MCU core in Verilog
150FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software
142training labs and examples
132RISC-V CPU Core
132Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
131SV/UVM based instruction generator for RISC-V processor verification
126Contains the code examples from The UVM Primer Book sorted by chapters.
93CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
80This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
79Reference examples and short projects using UVM Methodology
75This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
74Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
70Ultimate multigame cartridge for Nintendo Famicom
66SweRV EH1 core
65Source code repo for UVM Tutorial for Candy Lovers
55Verilog code for a simple synth module; developed on TinyFPGA BX
52AXI4 and AXI4-Lite interface definitions and testbench utilities
51Public repository for uEVB
48Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
1239 Followers 100+
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