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Top Star Repos
344Ariane is a 6-stage RISC-V CPU capable of booting Linux
328The root repo for lowRISC project and FPGA demos.
250An exploration of log domain "alternative floating point" for hardware ML/AI accelerators.
163A Verilog synthesis flow for Minecraft redstone circuits
149SCR1 is a high-quality open-source RISC-V MCU core in Verilog
142RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU
10832-bit RISC-V system on chip for iCE40 FPGAs
105RISC-V CPU Core
100Contains the code examples from The UVM Primer Book sorted by chapters.
93training labs and examples
88Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"
57This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
57CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
56Ultimate multigame cartridge for Nintendo Famicom
55Reference examples and short projects using UVM Methodology
53Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
43Source code repo for UVM Tutorial for Candy Lovers
40This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
39Hardware of sampling model
38Verilog code for a simple synth module; developed on TinyFPGA BX
38Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
35a playground for xilinx zynq fpga experiments
33RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
29WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
28Examples and reference for System Verilog Assertions
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