( New / Total ) * 100
( Update / Total ) * 100
|Sum stars of Top 30 repos
sum ( repos.stars )
|Fork 1000+ Repos
|Sum forks of Top 30 repos
sum ( repos.forks )
Top Star Repos
287Ariane is a 6-stage RISC-V CPU
284The root repo for lowRISC project and FPGA demos.
140A Verilog synthesis flow for Minecraft redstone circuits
113SCR1 is a high-quality open-source RISC-V MCU core in Verilog
101RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU
87Contains the code examples from The UVM Primer Book sorted by chapters.
85training labs and examples
74RISC-V CPU Core
6432-bit RISC-V system on chip for iCE40 FPGAs
49Reference examples and short projects using UVM Methodology
48Ultimate multigame cartridge for Nintendo Famicom
46CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
44Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
41This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
38Source code repo for UVM Tutorial for Candy Lovers
33Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
30a playground for xilinx zynq fpga experiments
28This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
28RISC-V port to Parallella Board
27Examples and reference for System Verilog Assertions
26SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)
25openHMC - an open source Hybrid Memory Cube Controller
23a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially
19Verilog code for a simple synth module; developed on TinyFPGA BX
19Advanced Encryption Standard (AES) SystemVerilog Core
817 Followers 100+
0 Repos per User
repos.Total / users.Total