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Top Star Repos
249The root repo for lowRISC project and FPGA demos.
243Ariane is a 6-stage RISC-V CPU
91SCR1 is an open-source RISC-V compatible MCU core
79training labs and examples
79A Verilog synthesis flow for Minecraft redstone circuits
72Contains the code examples from The UVM Primer Book sorted by chapters.
48RISC-V CPU Core
48Ultimate multigame cartridge for Nintendo Famicom
4432-bit RISC-V system on chip for iCE40 FPGAs
43Reference examples and short projects using UVM Methodology
34Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
32Source code repo for UVM Tutorial for Candy Lovers
31CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
30a playground for xilinx zynq fpga experiments
30This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
29Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
27RISC-V port to Parallella Board
25Examples and reference for System Verilog Assertions
24openHMC - an open source Hybrid Memory Cube Controller
21SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)
20a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially
17Advanced Encryption Standard (AES) SystemVerilog Core
16This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
16An attribute grammar-based programming language for composable language extensions
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