SystemVerilog

Updated : 2018-02-23 00:47:05 UTC

Respositories

Counts
Total

/search/repositories?q=language:SystemVerilog

2050
New

/search/repositories?q=language:SystemVerilog+created:2018-02-22

3
Increase rate

( New / Total ) * 100

0.15%
Activity
Update

/search/repositories?q=language:SystemVerilog+pushed:2018-02-22

20
Update Rate

( Update / Total ) * 100

0.98%
Sleeping

/search/repositories?q=language:SystemVerilog+pushed:<2017-02-22

981
Stars
Star 1000+

/search/repositories?q=language:SystemVerilog+stars:>=1000

0
Star 100+

/search/repositories?q=language:SystemVerilog+stars:>=100

2
Sum stars of Top 30 repos

sum ( repos.stars )

1359
Forks
Fork 1000+ Repos

/search/repositories?q=language:SystemVerilog+forks:>=1000

0
Fork 100+

/search/repositories?q=language:SystemVerilog+forks:>=100

0
Sum forks of Top 30 repos

sum ( repos.forks )

490

Top Star Repos

/search/repositories?q=language:SystemVerilog&sort=stars&order=desc&per_page=30

  1. 232
    The root repo for lowRISC project and FPGA demos.
  2. 209
    Ariane is a 6-stage RISC-V CPU
  3. 83
    SCR1 is an open-source RISC-V compatible MCU core
  4. 75
    A Verilog synthesis flow for Minecraft redstone circuits
  5. 74
    training labs and examples
  6. 66
    Contains the code examples from The UVM Primer Book sorted by chapters.
  1. 47
    Ultimate multigame cartridge for Nintendo Famicom
  2. 40
    Reference examples and short projects using UVM Methodology
  3. 37
    RISC-V CPU Core
  4. 33
    Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
  5. 31
    Source code repo for UVM Tutorial for Candy Lovers
  6. 30
    a playground for xilinx zynq fpga experiments
  7. 28
    Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  8. 26
    RISC-V port to Parallella Board
  9. 26
    Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
  10. 25
    openHMC - an open source Hybrid Memory Cube Controller
  11. 23
    Examples and reference for System Verilog Assertions
  12. 22
    UVM agents
  13. 22
    This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
  14. 21
    SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)
  15. 20
    a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially
  16. 17
    Advanced Encryption Standard (AES) SystemVerilog Core
  17. 17
    CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  18. 16
    An attribute grammar-based programming language for composable language extensions
  19. 13
    SystemVerilog VIP for AMBA APB protocol
  20. 12
    Replica of micro-BESM computer
  21. 12
    A high-throughput VHDL and SystemVerilog implementation of AES-128 including scripts for a full front-end design process.

New Repos

/search/repositories?q=language:SystemVerilog+created:2018-02-22&sort=stars&order=desc&per_page=12

Users

Total

/search/users?q=language:SystemVerilog

640
Followers 100+

/search/users?q=language:SystemVerilog+followers:>=100

0
Repos per User

repos.Total / users.Total

3.20