SystemVerilog

Updated : 2019-06-19 00:47:05 UTC

Respositories

Counts
Total

/search/repositories?q=language:SystemVerilog

3595
New

/search/repositories?q=language:SystemVerilog+created:2019-06-18

1
Increase rate

( New / Total ) * 100

0.03%
Activity
Update

/search/repositories?q=language:SystemVerilog+pushed:2019-06-18

19
Update Rate

( Update / Total ) * 100

0.53%
Sleeping

/search/repositories?q=language:SystemVerilog+pushed:<2018-06-18

2116
Stars
Star 1000+

/search/repositories?q=language:SystemVerilog+stars:>=1000

0
Star 100+

/search/repositories?q=language:SystemVerilog+stars:>=100

10
Sum stars of Top 30 repos

sum ( repos.stars )

3900
Forks
Fork 1000+ Repos

/search/repositories?q=language:SystemVerilog+forks:>=1000

0
Fork 100+

/search/repositories?q=language:SystemVerilog+forks:>=100

0
Sum forks of Top 30 repos

sum ( repos.forks )

1091

Top Star Repos

/search/repositories?q=language:SystemVerilog&sort=stars&order=desc&per_page=30

  1. 677
    A directory of Western Digital’s RISC-V SweRV Cores
  2. 486
    Ariane is a 6-stage RISC-V CPU capable of booting Linux
  3. 392
    The root repo for lowRISC project and FPGA demos.
  4. 296
    An exploration of log domain "alternative floating point" for hardware ML/AI accelerators.
  5. 232
    A Verilog synthesis flow for Minecraft redstone circuits
  6. 212
    RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU
  1. 193
    SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  2. 127
    training labs and examples
  3. 125
    RISC-V CPU Core
  4. 117
    Contains the code examples from The UVM Primer Book sorted by chapters.
  5. 82
    CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  6. 75
    Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
  7. 67
    Reference examples and short projects using UVM Methodology
  8. 67
    This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
  9. 65
    Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
  10. 59
    Ultimate multigame cartridge for Nintendo Famicom
  11. 56
    This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
  12. 54
    Source code repo for UVM Tutorial for Candy Lovers
  13. 49
    Verilog code for a simple synth module; developed on TinyFPGA BX
  14. 44
    Public repository for uEVB
  15. 44
    Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
  16. 41
    AXI4 and AXI4-Lite interface definitions and testbench utilities
  17. 40
    a playground for xilinx zynq fpga experiments
  18. 40
    High performance embedded systems debug/reverse engineering platform
  19. 39
    Hardware of sampling model
  20. 39
    WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
  21. 37
    RISC-V Rocket Core on Parallella &amp; ZedBoard Zynq FPGA Boards

New Repos

/search/repositories?q=language:SystemVerilog+created:2019-06-18&sort=stars&order=desc&per_page=12

Users

Total

/search/users?q=language:SystemVerilog

1093
Followers 100+

/search/users?q=language:SystemVerilog+followers:>=100

0
Repos per User

repos.Total / users.Total

3.29