SystemVerilog

Updated : 2019-04-20 00:47:04 UTC

Respositories

Counts
Total

/search/repositories?q=language:SystemVerilog

3392
New

/search/repositories?q=language:SystemVerilog+created:2019-04-19

7
Increase rate

( New / Total ) * 100

0.21%
Activity
Update

/search/repositories?q=language:SystemVerilog+pushed:2019-04-19

20
Update Rate

( Update / Total ) * 100

0.59%
Sleeping

/search/repositories?q=language:SystemVerilog+pushed:<2018-04-19

1920
Stars
Star 1000+

/search/repositories?q=language:SystemVerilog+stars:>=1000

0
Star 100+

/search/repositories?q=language:SystemVerilog+stars:>=100

10
Sum stars of Top 30 repos

sum ( repos.stars )

3571
Forks
Fork 1000+ Repos

/search/repositories?q=language:SystemVerilog+forks:>=1000

0
Fork 100+

/search/repositories?q=language:SystemVerilog+forks:>=100

0
Sum forks of Top 30 repos

sum ( repos.forks )

991

Top Star Repos

/search/repositories?q=language:SystemVerilog&sort=stars&order=desc&per_page=30

  1. 648
    A directory of Western Digital’s RISC-V SweRV Cores
  2. 439
    Ariane is a 6-stage RISC-V CPU capable of booting Linux
  3. 372
    The root repo for lowRISC project and FPGA demos.
  4. 285
    An exploration of log domain "alternative floating point" for hardware ML/AI accelerators.
  5. 188
    A Verilog synthesis flow for Minecraft redstone circuits
  6. 186
    SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  1. 184
    RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU
  2. 121
    RISC-V CPU Core
  3. 113
    training labs and examples
  4. 110
    Contains the code examples from The UVM Primer Book sorted by chapters.
  5. 72
    CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  6. 63
    This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
  7. 62
    Reference examples and short projects using UVM Methodology
  8. 61
    Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
  9. 57
    Ultimate multigame cartridge for Nintendo Famicom
  10. 52
    This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
  11. 50
    Source code repo for UVM Tutorial for Candy Lovers
  12. 47
    Verilog code for a simple synth module; developed on TinyFPGA BX
  13. 41
    Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
  14. 40
    a playground for xilinx zynq fpga experiments
  15. 39
    Hardware of sampling model
  16. 38
    High performance embedded systems debug/reverse engineering platform
  17. 37
    WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
  18. 37
    RISC-V Rocket Core on Parallella &amp; ZedBoard Zynq FPGA Boards
  19. 35
    AXI4 and AXI4-Lite interface definitions and testbench utilities
  20. 29
    FX68K 68000 cycle accurate SystemVerilog core

New Repos

/search/repositories?q=language:SystemVerilog+created:2019-04-19&sort=stars&order=desc&per_page=12

Users

Total

/search/users?q=language:SystemVerilog

1024
Followers 100+

/search/users?q=language:SystemVerilog+followers:>=100

0
Repos per User

repos.Total / users.Total

3.31