SystemVerilog

Updated : 2018-10-23 00:47:00 UTC

Respositories

Counts
Total

/search/repositories?q=language:SystemVerilog

2780
New

/search/repositories?q=language:SystemVerilog+created:2018-10-22

2
Increase rate

( New / Total ) * 100

0.07%
Activity
Update

/search/repositories?q=language:SystemVerilog+pushed:2018-10-22

21
Update Rate

( Update / Total ) * 100

0.76%
Sleeping

/search/repositories?q=language:SystemVerilog+pushed:<2017-10-22

1471
Stars
Star 1000+

/search/repositories?q=language:SystemVerilog+stars:>=1000

0
Star 100+

/search/repositories?q=language:SystemVerilog+stars:>=100

5
Sum stars of Top 30 repos

sum ( repos.stars )

2142
Forks
Fork 1000+ Repos

/search/repositories?q=language:SystemVerilog+forks:>=1000

0
Fork 100+

/search/repositories?q=language:SystemVerilog+forks:>=100

0
Sum forks of Top 30 repos

sum ( repos.forks )

735

Top Star Repos

/search/repositories?q=language:SystemVerilog&sort=stars&order=desc&per_page=30

  1. 316
    Ariane is a 6-stage RISC-V CPU
  2. 311
    The root repo for lowRISC project and FPGA demos.
  3. 149
    A Verilog synthesis flow for Minecraft redstone circuits
  4. 132
    SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  5. 123
    RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU
  6. 95
    Contains the code examples from The UVM Primer Book sorted by chapters.
  1. 92
    RISC-V CPU Core
  2. 91
    training labs and examples
  3. 90
    32-bit RISC-V system on chip for iCE40 FPGAs
  4. 55
    Ultimate multigame cartridge for Nintendo Famicom
  5. 54
    This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
  6. 52
    Reference examples and short projects using UVM Methodology
  7. 52
    Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
  8. 50
    CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  9. 40
    Hardware of sampling model
  10. 40
    Source code repo for UVM Tutorial for Candy Lovers
  11. 36
    Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
  12. 35
    This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
  13. 35
    Verilog code for a simple synth module; developed on TinyFPGA BX
  14. 32
    RISC-V port to Parallella Board
  15. 31
    a playground for xilinx zynq fpga experiments
  16. 28
    Examples and reference for System Verilog Assertions
  17. 26
    openHMC - an open source Hybrid Memory Cube Controller
  18. 26
    SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)
  19. 24
    UVM agents
  20. 24
    WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
  21. 24
    a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially
  22. 19
    Advanced Encryption Standard (AES) SystemVerilog Core

New Repos

/search/repositories?q=language:SystemVerilog+created:2018-10-22&sort=stars&order=desc&per_page=12

Users

Total

/search/users?q=language:SystemVerilog

864
Followers 100+

/search/users?q=language:SystemVerilog+followers:>=100

0
Repos per User

repos.Total / users.Total

3.22