SystemVerilog

Updated : 2019-12-11 00:56:36 UTC

Respositories

Counts
Total

/search/repositories?q=language:SystemVerilog

4264
New

/search/repositories?q=language:SystemVerilog+created:2019-12-10

4
Increase rate

( New / Total ) * 100

0.09%
Activity
Update

/search/repositories?q=language:SystemVerilog+pushed:2019-12-10

31
Update Rate

( Update / Total ) * 100

0.73%
Sleeping

/search/repositories?q=language:SystemVerilog+pushed:<2018-12-10

2487
Stars
Star 1000+

/search/repositories?q=language:SystemVerilog+stars:>=1000

0
Star 100+

/search/repositories?q=language:SystemVerilog+stars:>=100

16
Sum stars of Top 30 repos

sum ( repos.stars )

5588
Forks
Fork 1000+ Repos

/search/repositories?q=language:SystemVerilog+forks:>=1000

0
Fork 100+

/search/repositories?q=language:SystemVerilog+forks:>=100

2
Sum forks of Top 30 repos

sum ( repos.forks )

1542

Top Star Repos

/search/repositories?q=language:SystemVerilog&sort=stars&order=desc&per_page=30

  1. 710
    A directory of Western Digital’s RISC-V SweRV Cores
  2. 600
    Ariane is a 6-stage RISC-V CPU capable of booting Linux
  3. 451
    OpenTitan: Open source silicon root of trust
  4. 426
    The root repo for lowRISC project and FPGA demos.
  5. 320
    An exploration of log domain "alternative floating point" for hardware ML/AI accelerators.
  6. 290
    RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU
  1. 290
    NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
  2. 268
    A Verilog synthesis flow for Minecraft redstone circuits
  3. 246
    SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  4. 180
    SV/UVM based instruction generator for RISC-V processor verification
  5. 180
    Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
  6. 156
    FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software
  7. 150
    training labs and examples
  8. 134
    RISC-V CPU Core
  9. 132
    Contains the code examples from The UVM Primer Book sorted by chapters.
  10. 103
    CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  11. 91
    This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
  12. 89
    SweRV EH1 core
  13. 88
    This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
  14. 80
    Reference examples and short projects using UVM Methodology
  15. 77
    Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
  16. 71
    Ultimate multigame cartridge for Nintendo Famicom
  17. 67
    Source code repo for UVM Tutorial for Candy Lovers
  18. 64
    AXI4 and AXI4-Lite interface definitions and testbench utilities
  19. 58
    Verilog code for a simple synth module; developed on TinyFPGA BX
  20. 57
    WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
  21. 51
    Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
  22. 49
    FX68K 68000 cycle accurate SystemVerilog core

New Repos

/search/repositories?q=language:SystemVerilog+created:2019-12-10&sort=stars&order=desc&per_page=12

Users

Total

/search/users?q=language:SystemVerilog

1340
Followers 100+

/search/users?q=language:SystemVerilog+followers:>=100

0
Repos per User

repos.Total / users.Total

3.18