SystemVerilog

Updated : 2020-07-06 00:50:31 UTC

Respositories

Counts
Total

/search/repositories?q=language:SystemVerilog

5191
New

/search/repositories?q=language:SystemVerilog+created:2020-07-05

3
Increase rate

( New / Total ) * 100

0.06%
Activity
Update

/search/repositories?q=language:SystemVerilog+pushed:2020-07-05

20
Update Rate

( Update / Total ) * 100

0.39%
Sleeping

/search/repositories?q=language:SystemVerilog+pushed:<2019-07-05

3218
Stars
Star 1000+

/search/repositories?q=language:SystemVerilog+stars:>=1000

0
Star 100+

/search/repositories?q=language:SystemVerilog+stars:>=100

25
Sum stars of Top 30 repos

sum ( repos.stars )

7960
Forks
Fork 1000+ Repos

/search/repositories?q=language:SystemVerilog+forks:>=1000

0
Fork 100+

/search/repositories?q=language:SystemVerilog+forks:>=100

10
Sum forks of Top 30 repos

sum ( repos.forks )

2316

Top Star Repos

/search/repositories?q=language:SystemVerilog&sort=stars&order=desc&per_page=30

  1. 767
    The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
  2. 748
    A directory of Western Digital’s RISC-V SweRV Cores
  3. 710
    OpenTitan: Open source silicon root of trust
  4. 471
    The root repo for lowRISC project and FPGA demos.
  5. 385
    Send video/audio over HDMI on an FPGA
  6. 363
    CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  1. 360
    NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
  2. 337
    An exploration of log domain &quot;alternative floating point&quot; for hardware ML/AI accelerators.
  3. 328
    Proving leftpad correct in a dozen different ways
  4. 314
    SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  5. 310
    A Verilog synthesis flow for Minecraft redstone circuits
  6. 308
    Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
  7. 303
    SV/UVM based instruction generator for RISC-V processor verification
  8. 237
    Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.
  9. 210
    SweRV EH1 core
  10. 193
    FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software
  11. 169
    training labs and examples
  12. 164
    RSD: RISC-V Out-of-Order Superscalar Processor
  13. 157
    Contains the code examples from The UVM Primer Book sorted by chapters.
  14. 142
    RISC-V CPU Core
  15. 126
    AXI4 and AXI4-Lite synthesizable modules and verification infrastructure
  16. 125
    CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  17. 113
    This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
  18. 111
    This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
  19. 101
    Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
  20. 98
    Reference examples and short projects using UVM Methodology
  21. 82
    Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
  22. 78
    Ultimate multigame cartridge for Nintendo Famicom
  23. 77
    Source code repo for UVM Tutorial for Candy Lovers
  24. 73
    Verilog code for a simple synth module; developed on TinyFPGA BX

New Repos

/search/repositories?q=language:SystemVerilog+created:2020-07-05&sort=stars&order=desc&per_page=12

Users

Total

/search/users?q=language:SystemVerilog

1737
Followers 100+

/search/users?q=language:SystemVerilog+followers:>=100

0
Repos per User

repos.Total / users.Total

2.99