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Top Star Repos
274Ariane is a 6-stage RISC-V CPU
261The root repo for lowRISC project and FPGA demos.
102SCR1 is an open-source RISC-V compatible MCU core
87A Verilog synthesis flow for Minecraft redstone circuits
85RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU
81Contains the code examples from The UVM Primer Book sorted by chapters.
79training labs and examples
61RISC-V CPU Core
5832-bit RISC-V system on chip for iCE40 FPGAs
46Reference examples and short projects using UVM Methodology
46Ultimate multigame cartridge for Nintendo Famicom
38Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
37CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
36This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
36Source code repo for UVM Tutorial for Candy Lovers
32Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
30a playground for xilinx zynq fpga experiments
28RISC-V port to Parallella Board
26Examples and reference for System Verilog Assertions
25openHMC - an open source Hybrid Memory Cube Controller
23This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
22SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)
22a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially
17Advanced Encryption Standard (AES) SystemVerilog Core
17An attribute grammar-based programming language for composable language extensions
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