SystemVerilog

Updated : 2018-06-22 00:47:09 UTC

Respositories

Counts
Total

/search/repositories?q=language:SystemVerilog

2441
New

/search/repositories?q=language:SystemVerilog+created:2018-06-21

1
Increase rate

( New / Total ) * 100

0.04%
Activity
Update

/search/repositories?q=language:SystemVerilog+pushed:2018-06-21

22
Update Rate

( Update / Total ) * 100

0.90%
Sleeping

/search/repositories?q=language:SystemVerilog+pushed:<2017-06-21

1269
Stars
Star 1000+

/search/repositories?q=language:SystemVerilog+stars:>=1000

0
Star 100+

/search/repositories?q=language:SystemVerilog+stars:>=100

3
Sum stars of Top 30 repos

sum ( repos.stars )

1670
Forks
Fork 1000+ Repos

/search/repositories?q=language:SystemVerilog+forks:>=1000

0
Fork 100+

/search/repositories?q=language:SystemVerilog+forks:>=100

0
Sum forks of Top 30 repos

sum ( repos.forks )

575

Top Star Repos

/search/repositories?q=language:SystemVerilog&sort=stars&order=desc&per_page=30

  1. 274
    Ariane is a 6-stage RISC-V CPU
  2. 261
    The root repo for lowRISC project and FPGA demos.
  3. 102
    SCR1 is an open-source RISC-V compatible MCU core
  4. 87
    A Verilog synthesis flow for Minecraft redstone circuits
  5. 85
    RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU
  6. 81
    Contains the code examples from The UVM Primer Book sorted by chapters.
  1. 79
    training labs and examples
  2. 61
    RISC-V CPU Core
  3. 58
    32-bit RISC-V system on chip for iCE40 FPGAs
  4. 46
    Reference examples and short projects using UVM Methodology
  5. 46
    Ultimate multigame cartridge for Nintendo Famicom
  6. 38
    Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
  7. 37
    CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  8. 36
    This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
  9. 36
    Source code repo for UVM Tutorial for Candy Lovers
  10. 32
    Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
  11. 30
    a playground for xilinx zynq fpga experiments
  12. 28
    RISC-V port to Parallella Board
  13. 26
    Examples and reference for System Verilog Assertions
  14. 25
    openHMC - an open source Hybrid Memory Cube Controller
  15. 24
    UVM agents
  16. 23
    This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
  17. 22
    SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)
  18. 22
    a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially
  19. 17
    Advanced Encryption Standard (AES) SystemVerilog Core
  20. 17
    An attribute grammar-based programming language for composable language extensions
  21. 15
    ZX Spectrum 128K for MIST Board
  22. 14
    Replica of micro-BESM computer

New Repos

/search/repositories?q=language:SystemVerilog+created:2018-06-21&sort=stars&order=desc&per_page=12

Users

Total

/search/users?q=language:SystemVerilog

779
Followers 100+

/search/users?q=language:SystemVerilog+followers:>=100

0
Repos per User

repos.Total / users.Total

3.13