SystemVerilog

Updated : 2020-01-29 00:50:37 UTC

Respositories

Counts
Total

/search/repositories?q=language:SystemVerilog

4439
New

/search/repositories?q=language:SystemVerilog+created:2020-01-28

3
Increase rate

( New / Total ) * 100

0.07%
Activity
Update

/search/repositories?q=language:SystemVerilog+pushed:2020-01-28

27
Update Rate

( Update / Total ) * 100

0.61%
Sleeping

/search/repositories?q=language:SystemVerilog+pushed:<2019-01-28

2654
Stars
Star 1000+

/search/repositories?q=language:SystemVerilog+stars:>=1000

0
Star 100+

/search/repositories?q=language:SystemVerilog+stars:>=100

20
Sum stars of Top 30 repos

sum ( repos.stars )

6286
Forks
Fork 1000+ Repos

/search/repositories?q=language:SystemVerilog+forks:>=1000

0
Fork 100+

/search/repositories?q=language:SystemVerilog+forks:>=100

4
Sum forks of Top 30 repos

sum ( repos.forks )

1698

Top Star Repos

/search/repositories?q=language:SystemVerilog&sort=stars&order=desc&per_page=30

  1. 734
    A directory of Western Digital’s RISC-V SweRV Cores
  2. 647
    Ariane is a 6-stage RISC-V CPU capable of booting Linux
  3. 554
    OpenTitan: Open source silicon root of trust
  4. 440
    The root repo for lowRISC project and FPGA demos.
  5. 324
    An exploration of log domain "alternative floating point" for hardware ML/AI accelerators.
  6. 315
    RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU
  1. 308
    NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
  2. 274
    A Verilog synthesis flow for Minecraft redstone circuits
  3. 263
    SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  4. 214
    Proving leftpad correct in a dozen different ways
  5. 211
    SV/UVM based instruction generator for RISC-V processor verification
  6. 205
    Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
  7. 164
    FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software
  8. 154
    training labs and examples
  9. 136
    RISC-V CPU Core
  10. 136
    Contains the code examples from The UVM Primer Book sorted by chapters.
  11. 136
    SweRV EH1 core
  12. 119
    RSD: RISC-V Out-of-Order Superscalar Processor
  13. 110
    CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  14. 101
    This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
  15. 93
    This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
  16. 84
    Reference examples and short projects using UVM Methodology
  17. 78
    Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
  18. 76
    AXI4 and AXI4-Lite interface definitions and testbench utilities
  19. 72
    Ultimate multigame cartridge for Nintendo Famicom
  20. 67
    Source code repo for UVM Tutorial for Candy Lovers
  21. 62
    WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
  22. 58
    Verilog code for a simple synth module; developed on TinyFPGA BX

New Repos

/search/repositories?q=language:SystemVerilog+created:2020-01-28&sort=stars&order=desc&per_page=12

Users

Total

/search/users?q=language:SystemVerilog

1406
Followers 100+

/search/users?q=language:SystemVerilog+followers:>=100

0
Repos per User

repos.Total / users.Total

3.16