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Top Star Repos
710A directory of Western Digital’s RISC-V SweRV Cores
600Ariane is a 6-stage RISC-V CPU capable of booting Linux
451OpenTitan: Open source silicon root of trust
426The root repo for lowRISC project and FPGA demos.
320An exploration of log domain "alternative floating point" for hardware ML/AI accelerators.
290RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU
290NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
268A Verilog synthesis flow for Minecraft redstone circuits
246SCR1 is a high-quality open-source RISC-V MCU core in Verilog
180SV/UVM based instruction generator for RISC-V processor verification
180Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
156FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software
150training labs and examples
134RISC-V CPU Core
132Contains the code examples from The UVM Primer Book sorted by chapters.
103CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
91This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
89SweRV EH1 core
88This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
80Reference examples and short projects using UVM Methodology
77Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
71Ultimate multigame cartridge for Nintendo Famicom
67Source code repo for UVM Tutorial for Candy Lovers
64AXI4 and AXI4-Lite interface definitions and testbench utilities
58Verilog code for a simple synth module; developed on TinyFPGA BX
57WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
1340 Followers 100+
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