SystemVerilog

Updated : 2019-10-18 00:44:00 UTC

Respositories

Counts
Total

/search/repositories?q=language:SystemVerilog

4012
New

/search/repositories?q=language:SystemVerilog+created:2019-10-17

3
Increase rate

( New / Total ) * 100

0.07%
Activity
Update

/search/repositories?q=language:SystemVerilog+pushed:2019-10-17

19
Update Rate

( Update / Total ) * 100

0.47%
Sleeping

/search/repositories?q=language:SystemVerilog+pushed:<2018-10-17

2346
Stars
Star 1000+

/search/repositories?q=language:SystemVerilog+stars:>=1000

0
Star 100+

/search/repositories?q=language:SystemVerilog+stars:>=100

14
Sum stars of Top 30 repos

sum ( repos.stars )

4779
Forks
Fork 1000+ Repos

/search/repositories?q=language:SystemVerilog+forks:>=1000

0
Fork 100+

/search/repositories?q=language:SystemVerilog+forks:>=100

1
Sum forks of Top 30 repos

sum ( repos.forks )

1364

Top Star Repos

/search/repositories?q=language:SystemVerilog&sort=stars&order=desc&per_page=30

  1. 705
    A directory of Western Digital’s RISC-V SweRV Cores
  2. 558
    Ariane is a 6-stage RISC-V CPU capable of booting Linux
  3. 407
    The root repo for lowRISC project and FPGA demos.
  4. 312
    An exploration of log domain "alternative floating point" for hardware ML/AI accelerators.
  5. 260
    RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU
  6. 255
    A Verilog synthesis flow for Minecraft redstone circuits
  1. 253
    NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
  2. 226
    SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  3. 150
    FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software
  4. 142
    training labs and examples
  5. 132
    RISC-V CPU Core
  6. 132
    Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
  7. 131
    SV/UVM based instruction generator for RISC-V processor verification
  8. 126
    Contains the code examples from The UVM Primer Book sorted by chapters.
  9. 93
    CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  10. 80
    This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
  11. 79
    Reference examples and short projects using UVM Methodology
  12. 75
    This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
  13. 74
    Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
  14. 70
    Ultimate multigame cartridge for Nintendo Famicom
  15. 66
    SweRV EH1 core
  16. 65
    Source code repo for UVM Tutorial for Candy Lovers
  17. 55
    Verilog code for a simple synth module; developed on TinyFPGA BX
  18. 52
    AXI4 and AXI4-Lite interface definitions and testbench utilities
  19. 51
    Public repository for uEVB
  20. 48
    Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
  21. 44
    FX68K 68000 cycle accurate SystemVerilog core
  22. 44
    RISC-V Rocket Core on Parallella &amp; ZedBoard Zynq FPGA Boards

New Repos

/search/repositories?q=language:SystemVerilog+created:2019-10-17&sort=stars&order=desc&per_page=12

Users

Total

/search/users?q=language:SystemVerilog

1239
Followers 100+

/search/users?q=language:SystemVerilog+followers:>=100

0
Repos per User

repos.Total / users.Total

3.24