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Top Star Repos
767The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
748A directory of Western Digital’s RISC-V SweRV Cores
710OpenTitan: Open source silicon root of trust
471The root repo for lowRISC project and FPGA demos.
385Send video/audio over HDMI on an FPGA
363CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
360NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
337An exploration of log domain "alternative floating point" for hardware ML/AI accelerators.
328Proving leftpad correct in a dozen different ways
314SCR1 is a high-quality open-source RISC-V MCU core in Verilog
310A Verilog synthesis flow for Minecraft redstone circuits
308Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
303SV/UVM based instruction generator for RISC-V processor verification
237Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.
210SweRV EH1 core
193FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software
169training labs and examples
164RSD: RISC-V Out-of-Order Superscalar Processor
157Contains the code examples from The UVM Primer Book sorted by chapters.
142RISC-V CPU Core
126AXI4 and AXI4-Lite synthesizable modules and verification infrastructure
125CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
113This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
111This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
101Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
98Reference examples and short projects using UVM Methodology
82Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
1737 Followers 100+
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