( New / Total ) * 100
( Update / Total ) * 100
|Sum stars of Top 30 repos
sum ( repos.stars )
|Fork 1000+ Repos
|Sum forks of Top 30 repos
sum ( repos.forks )
Top Star Repos
691A directory of Western Digital’s RISC-V SweRV Cores
522Ariane is a 6-stage RISC-V CPU capable of booting Linux
398The root repo for lowRISC project and FPGA demos.
303An exploration of log domain "alternative floating point" for hardware ML/AI accelerators.
246A Verilog synthesis flow for Minecraft redstone circuits
236RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU
204SCR1 is a high-quality open-source RISC-V MCU core in Verilog
137training labs and examples
130RISC-V CPU Core
121Contains the code examples from The UVM Primer Book sorted by chapters.
107Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
103SV/UVM based open-source instruction generator for RISC-V processor verification
89CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
75This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
71Reference examples and short projects using UVM Methodology
71Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
68This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
66Ultimate multigame cartridge for Nintendo Famicom
58Source code repo for UVM Tutorial for Candy Lovers
53Verilog code for a simple synth module; developed on TinyFPGA BX
46Public repository for uEVB
45AXI4 and AXI4-Lite interface definitions and testbench utilities
44Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
42SweRV EH1 core
40a playground for xilinx zynq fpga experiments
1163 Followers 100+
0 Repos per User
repos.Total / users.Total