SystemVerilog

Updated : 2019-02-23 00:46:59 UTC

Respositories

Counts
Total

/search/repositories?q=language:SystemVerilog

3188
New

/search/repositories?q=language:SystemVerilog+created:2019-02-22

4
Increase rate

( New / Total ) * 100

0.13%
Activity
Update

/search/repositories?q=language:SystemVerilog+pushed:2019-02-22

23
Update Rate

( Update / Total ) * 100

0.72%
Sleeping

/search/repositories?q=language:SystemVerilog+pushed:<2018-02-22

1757
Stars
Star 1000+

/search/repositories?q=language:SystemVerilog+stars:>=1000

0
Star 100+

/search/repositories?q=language:SystemVerilog+stars:>=100

11
Sum stars of Top 30 repos

sum ( repos.stars )

3343
Forks
Fork 1000+ Repos

/search/repositories?q=language:SystemVerilog+forks:>=1000

0
Fork 100+

/search/repositories?q=language:SystemVerilog+forks:>=100

0
Sum forks of Top 30 repos

sum ( repos.forks )

903

Top Star Repos

/search/repositories?q=language:SystemVerilog&sort=stars&order=desc&per_page=30

  1. 589
    A directory of Western Digital’s RISC-V SweRV Cores
  2. 390
    Ariane is a 6-stage RISC-V CPU capable of booting Linux
  3. 354
    The root repo for lowRISC project and FPGA demos.
  4. 272
    An exploration of log domain "alternative floating point" for hardware ML/AI accelerators.
  5. 173
    A Verilog synthesis flow for Minecraft redstone circuits
  6. 165
    RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU
  1. 165
    SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  2. 113
    RISC-V CPU Core
  3. 104
    Spatial: &quot;Specify Parameterized Accelerators Through Inordinately Abstract Language&quot;
  4. 103
    Contains the code examples from The UVM Primer Book sorted by chapters.
  5. 100
    training labs and examples
  6. 66
    CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  7. 62
    This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
  8. 58
    Reference examples and short projects using UVM Methodology
  9. 57
    Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
  10. 56
    Ultimate multigame cartridge for Nintendo Famicom
  11. 47
    Source code repo for UVM Tutorial for Candy Lovers
  12. 46
    This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
  13. 41
    Verilog code for a simple synth module; developed on TinyFPGA BX
  14. 39
    a playground for xilinx zynq fpga experiments
  15. 39
    Hardware of sampling model
  16. 39
    Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
  17. 36
    RISC-V Rocket Core on Parallella &amp; ZedBoard Zynq FPGA Boards
  18. 32
    High performance embedded systems debug/reverse engineering platform
  19. 31
    WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
  20. 28
    Examples and reference for System Verilog Assertions
  21. 27
    UVM agents

New Repos

/search/repositories?q=language:SystemVerilog+created:2019-02-22&sort=stars&order=desc&per_page=12

Users

Total

/search/users?q=language:SystemVerilog

972
Followers 100+

/search/users?q=language:SystemVerilog+followers:>=100

0
Repos per User

repos.Total / users.Total

3.28