Updated : 2019-12-14 00:14:16 UTC

Respositories

Counts
Total

/search/repositories?q=language:Bluespec

161
New

/search/repositories?q=language:Bluespec+created:2019-12-13

0
Increase rate

( New / Total ) * 100

0.00%
Activity
Update

/search/repositories?q=language:Bluespec+pushed:2019-12-13

1
Update Rate

( Update / Total ) * 100

0.62%
Sleeping

/search/repositories?q=language:Bluespec+pushed:<2018-12-13

117
Stars
Star 1000+

/search/repositories?q=language:Bluespec+stars:>=1000

0
Star 100+

/search/repositories?q=language:Bluespec+stars:>=100

0
Sum stars of Top 30 repos

sum ( repos.stars )

509
Forks
Fork 1000+ Repos

/search/repositories?q=language:Bluespec+forks:>=1000

0
Fork 100+

/search/repositories?q=language:Bluespec+forks:>=100

0
Sum forks of Top 30 repos

sum ( repos.forks )

207

Top Star Repos

/search/repositories?q=language:Bluespec&sort=stars&order=desc&per_page=30

  1. 97
    Connectal is a framework for software-driven hardware development.
  2. 44
    Riscy Processors - Open-Sourced RISC-V Processors
  3. 41
    P4-14/16 Bluespec Compiler
  4. 39
    RiscyOO: RISC-V Out-of-Order Processor
  5. 33
    The BERI and CHERI processor and hardware platform
  6. 24
    Open Source SSD Controller. NVMe and Lightstor variants
  1. 20
    MAERI public release
  2. 20
    PCIe library for the Xilinx 7 series FPGAs in the Bluespec language
  3. 18
    Bluespec BSV HLHDL tutorial
  4. 17
    A generic test bench written in Bluespec
  5. 17
    MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  6. 16
    A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)
  7. 15
    Public release
  8. 13
    OGC Points of Interest Encoding Specification
  9. 11
    RISC-V BSV Specification
  10. 9
    P4FPGA is located at github.com/hanw/p4fpga
  11. 8
    Manythread overlay for FPGA clusters
  12. 8
    Bluespec SystemVerilog library for use of the IBM Coherent Accelerator-Processor Interface (CAPI)
  13. 8
    Lab code for three-day lecture, &quot;Designing CNN Accelerators using Bluespec System Verilog&quot;, given at SNU in December 2017
  14. 7
    Rapid system integration of high-level synthesis kernels using the LEAP FPGA framework
  15. 7
    BlueDBM hw/sw implementation using the bluespecpcie PCIe library
  16. 6
    Bluespec SystemVerilog Reed Solomon Decoder
  17. 5
    A Bluespec SystemVerilog library of miscellaneous components
  18. 4
    A Network Architecture for Disaggregated Racks
  19. 4
    Bluespec System Verilog language extension for Visual Studio Code
  20. 4
    LEAP FPGA primary components
  21. 4
    Bluespec H.264 Decoder
  22. 4
    Structural Spec parser based on Bluespec
  23. 3
    Bluespec 802.11a Transmitter
  24. 3
    Bluespec ISA Description framework

New Repos

/search/repositories?q=language:Bluespec+created:2019-12-13&sort=stars&order=desc&per_page=12

Users

Total

/search/users?q=language:Bluespec

52
Followers 100+

/search/users?q=language:Bluespec+followers:>=100

0
Repos per User

repos.Total / users.Total

3.10